Implementation of High-Resolution and Area-Efficient FPGA Programmable Delay Lines
碩士 === 國立臺灣大學 === 電子工程學研究所 === 103 === In this work, the high area-efficient and high-resolution programmable delay line that can be implemented on FPGA is proposed. We also proposed high area-efficient delay cells based on FPGA architecture. Using the different characteristics of these delay cells...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/00619650833227534348 |