| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 103 === RTL (Register Transaction Level) design debugging and verification is always a challenging problem. Traditionally, the research of debugging used to insert MUX (Multiplexer) into design to find the bugs. However, because of the complexity and designer’s design knowledge of RTL design, most engineers used to use waveform tools (e.g. Verdi) with design knowledge to debug rather than using automatic debugging tool. Combining the human’s behavior and knowledge on debugging and verification is a good perspective to research.
We proposes a new approach and builds a system to debug RTL design by introducing formal semantic model and inference with design knowledge just like what designers used to do. With semantic of RTL code, design knowledge, we can easily infer what may cause these bugs. Also, we can use this semantic model and design knowledge to automatically write assertion and monitor into design. Finally, we point out the strengths and weaknesses of this approach, and possibilities on future research to improve our system.
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