RTL Design Debugging and Verification by Formal Semantic Modeling and Inference of Design Knowledge
碩士 === 國立臺灣大學 === 電機工程學研究所 === 103 === RTL (Register Transaction Level) design debugging and verification is always a challenging problem. Traditionally, the research of debugging used to insert MUX (Multiplexer) into design to find the bugs. However, because of the complexity and designer’s des...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/98589654600987059328 |