Design of 24-GHz CMOS Balanced Divide-by-3 Injection-Locked Frequency Dividers and Their Applications to Implement Divide-by-24 Frequency Dividers
碩士 === 國立臺灣科技大學 === 電子工程系 === 103 === This thesis presents the frequency divider links for the 24-GHz phase-locked loop application. The developed frequency divider links are designed and fabricated using the TSMC 0.18 μm CMOS process. The balanced divide-by-3 injection-locked frequency divider (ILF...
Main Authors: | Sung-Hao Cheng, 程嵩浩 |
---|---|
Other Authors: | Chao-Hsiung Tseng |
Format: | Others |
Language: | zh-TW |
Published: |
2015
|
Online Access: | http://ndltd.ncl.edu.tw/handle/42150966587404260132 |
Similar Items
-
Dual-mode Divide-by-3/-5 Direct Injection-Locked Frequency Divider and 24 GHz PLL in a CMOS Process
by: Sih-HanLi, et al.
Published: (2011) -
Design of 24-GHz CMOS VCO and 24-/60-GHz Frequency Divider
by: Yi-tsung Chen, et al.
Published: (2009) -
Design and Implementation of W-Band CMOS Divide-by-3 Injection-Locked Frequency Divider (ILFD)
by: SU,BO-RONG, et al.
Published: (2017) -
Design of Injection-Locked Frequency Dividers in CMOS Technology
by: Jia-Hao Ye, et al.
Published: (2011) -
Oscillator and Divide-by 2 Injection-Locked Frequency Divider
by: Yu-Wen Huang, et al.
Published: (2018)