| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 103 === First, a triple-band divide-by-3 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-3 ILFD use a cross-coupled nMOS pair and a 6th order RLC resonator with three resonant frequencies. The ILFD has three oscillation frequency bands and three locking ranges, which can be measured at fixed tuning bias and tuning bias. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm the high-band, middle-band and low-band locking range of the divide-by-3 ILFD are, respectively, 3.47GHz (33.87％) from 8.51 to 11.98 GHz, 3.72GHz (54.86％) from 4.92 to 8.64 GHz and 1.05GHz (19.76％) from 4.88 to 5.93 GHz. The largest locking range is given by 4.43GHz (67.07%) from 4.39 to 8.82 GHz. The core power consumption is 6.759 mW. The die area is 0.991×1.045 mm2.
Secondly, the divide-by-3 ILFD uses a single-ended injection signal, a cross-coupled nMOS pair and an injection MOSFET. The divide-by-3 ILFD has three oscillation frequency bands and three locking ranges via varactor control voltage. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm the high-band, middle-band and low-band locking range of the divide-by-3 ILFD are, respectively, given by 3.05GHz (30.70％) from 8.41 to 11.46 GHz, 3.28GHz (46.59％) from 5.40 to 8.68 GHz and 0.99GHz (18.77％) from 4.78 to 5.77 GHz. The operation range is 6.68GHz, extending from 4.78 to 11.46 GHz.
Finally, a wide-band divide-by-2 LC injection-locked frequency divider was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 ILFD uses a cross-coupled nMOS pair and a 6th order RLC resonator. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm, the maximum locking range of the divide-by-2 ILFD is 5.77GHz (105.2％) from 2.6 to 8.37 GHz, and the operation range is 6.71GHz (124.14％) from 2.05 to 8.76 GHz via varactor switching. The core power consumption is 6.76 mW.
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