| Summary: | 碩士 === 國立虎尾科技大學 === 電機工程研究所 === 103 === In this thesis, analysis and implementation of a low input current ripple KP Zeta dc converter which is based on KP dc converter proposed by National Tsing Hua University professor Ching-Tsai Pan in memory of his father Mr. Kung Pan (K.P.) . The proposed converter is added an auxiliary inductor and capacitor into the traditional Zeta converter. Basically, the method of reducing inductor current ripple is to increase inductor value or switching frequency. However, the two ways increase either volume and weight of the converter or switching loss. The proposed KP converter uses a new principle of zero inductor current ripple (ZICR). The proposed way is to make the voltage across the inductor in different operating modes approach to zero. As a result, the current through inductor can reach pure DC. It has advantages such as simple control and improvement for pulsating input current of the traditional Zeta converter. In ideal case, the converter can achieve zero input current ripple. A prototype with 100V input voltage, 66V to 122V output voltage and 180W rating is implemented. A maximum efficiency of 93% is achieved when the load is 60W. Finally, some experimental results and Bode plots verify the stability, ability of stepping up/down and low current ripple characteristics in CCM mode of the KP converter.
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