Algorithm and Architecture Design of Visibility Restoration for Real-World Hazy Scenes

博士 === 國立臺北科技大學 === 電子工程系博士班 === 103 === Visibility restoration methods are widely applied in computer vision-based systems used during inclement weather conditions. Object information in hazy images captured in these situations usually suffers from incomplete collection, which means that these obje...

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Bibliographic Details
Main Authors: Jian-Hui Ye, 葉建輝
Other Authors: Shih-Chia Huang
Format: Others
Language:en_US
Published: 2015
Online Access:http://ndltd.ncl.edu.tw/handle/4pr95d
Description
Summary:博士 === 國立臺北科技大學 === 電子工程系博士班 === 103 === Visibility restoration methods are widely applied in computer vision-based systems used during inclement weather conditions. Object information in hazy images captured in these situations usually suffers from incomplete collection, which means that these objects cannot be accurately detected by the computer vision-based systems. However, when color cast issues are present in an image - due to sandstorms, for instance - traditional haze removal techniques often result in inferior visibility restoration. Additionally, to achieve high-definition, real-time applications in computer vision systems, design of the hardware architecture for the visibility restoration is necessary and should be considered. This thesis presents a novel Laplacian-based haze removal method and its corresponding hardware architecture design to effectively overcome color cast issues and meet the requirement of real-time applications. Evaluation of the visibility restoration results via both qualitative and quantitative assessments demonstrate that the proposed Laplacian-based and hardware-oriented haze removal methods are capable of performing with satisfactory efficacy when compared with the results generated by other traditional haze removal techniques of real-world scenes captured during sandstorm conditions. Meanwhile, the proposed hardware architecture design can provide 64.52 MHz with 3.955 K logic elements. Simulation results indicate that the proposed hardware architecture design not only achieves the requirement of low hardware cost, but it also provides an average frame rate of 31.12 fps at image resolution 1080p (1920 × 1080).