Development of Copper Metallization Process Technology of Interdigitated Back Contact (100) Mono-crystalline Silicon Solar Cells

• Main Authors: Wei-Fan Liao, 廖偉帆
• Other Authors: Shyang-Jye Chang
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/n8a4k5

碩士 === 國立雲林科技大學 === 機械工程系 === 103 === This study is mainly to develop the copper metallization process technology of interdigitated back contact (100) mono-crystalline silicon solar cells (IBCSCs) which replaces the standard screen printing metallization process of silver (Ag) and aluminum (Al) pastes of conventional crystalline silicon solar cells for the low cost mass production application. In this study, all the processes needed were completed by using the standard IC and the crystalline silicon solar cells processes. The copper (Cu) metallization process was also demonstrated successfully by using the low cost copper electrochemical deposition (ECD) technology. Finally, all the characteristics of structure, material and photovoltaic of completed IBCSCs samples were measured and analyzed by SEM, EDS, XRD, UV-VIS-NIR spectrum, solar simulator and EQE, respectively. In this study, the research topics mainly include with (1) development of copper metallization process technology and (2) the study of photovoltaic characteristics of IBCSCs for different ions implantation concentration and depth of p+ emitter region and different minority carrier lifetime silicon wafer. The results were summarized as shown in the following. First, the Voc, fill factor (FF), and Jsc of IBCSCs samples made that the metallization process integrated with the nickel silicide, seed bi-layer of Al and Cu and Cu ECD were focused in the regions of 0.5999-0.6199 V, 76-81.5 % and 36-41 mA/cm2, respectively. Second, the Jsc of IBCSCs samples doped with an ion implantation concentration of 1021 atoms/cm3 in the p+ emitter region are higher than the ones doped with an ion implantation concentration of 5×1020 atoms/cm3 significantly. The enhancement of Jsc between the two IBCSCs samples is near 2-5 mA/cm2. In this study, the 6 inch, (100), n-type CZ silicon IC wafer with a minority carrier lifetime of 30 μs, a thickness of 200 μm and a resistivity (ρ) of 2-7 ohm-cm is used as the starting substrate to fabricate IBCSCs samples. For the best result, the efficiency, Voc, Jsc and fill factor (FF) of IBCSC sample with a p+/n+ emitter width ratio of 6:1 (p+/n+ emitter width=600 μm/100 μm), a contact hole opening ratio of 5 %, a NiSix/Al/Cu layers and a ECD Cu layer thickness of 5 μm are 19.99 %, 0.6199 V, 41.07 mA/cm2 and 78.52 %, respectively.