The design and implementation of the power supply for dynamic voltage and frequency scaling system
碩士 === 元智大學 === 電機工程學系 === 103 === This thesis presents a power supply for dynamic voltage and frequency scaling (DVFS) system. To verify its operation, a test digital circuit is served as the load of proposed power supply. To reduce power consumption of the digital circuit when it operate in the ta...
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| Format: | Others |
| Language: | zh-TW |
| Online Access: | http://ndltd.ncl.edu.tw/handle/g45rka |
| Summary: | 碩士 === 元智大學 === 電機工程學系 === 103 === This thesis presents a power supply for dynamic voltage and frequency scaling (DVFS) system. To verify its operation, a test digital circuit is served as the load of proposed power supply. To reduce power consumption of the digital circuit when it operate in the target frequency, this work tracks the operation of the digital circuits in the system and generates both the lowest supply voltage and operating clock signal for them. The proposed DC/DC Buck converter that generates the supply voltage for the digital circuit can track the lowest operating voltage dynamically. The operating clock signal for the digital circuit is generated from the phase-locked loop which can operate correctly with the same minimum supply voltage as the digital circuits.
A prototype chip for this work is fabricated in a standard TSMC 0.18μm 1P6M CMOS process with a chip area of 1.2 x1.2 mm2. When the standard supply voltage of the system is 1.8V, the simulation results show that 78.1% of power consumption for test digital circuit is reduced by utilizing the proposed power supply.
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