| Summary: | 碩士 === 國立中正大學 === 通訊工程研究所 === 104 === In recent years, MIMO technology plays an essential role in wireless communications. In the MIMO system, detection is a very important part of the baseband receiver. As the development of hard-output detection techniques becomes mature, emphasis of current studies are now on developing the soft-output detection techniques to provide soft-output information to subsequent channel decoder. In this thesis, parallel multiple tree traversals for the SDM-MIMO system to generate bit LLR (Log-Likelihood Ratio) values are considered. It is known that the ORVD decomposition of the channel matrix produces R-matrix with pair-wise entries. This property is exploited in our design to produce parallel processing units in our architecture. For the 256-QAM signals and 4-by 4 antenna configuration in this thesis, a total of 64 candidates is searched by each of the 4 parallel tree traversals. Our architecture produces 8 candidates per clock cycle, indicating a total of 8 clock cycles is required to output the 64 candidates. To compute the bit LLR values, we propose two methods to find the minimum of the metrics of the 64 candidates. Method 1 waits until all the 64 candidates are output and then finds the minimum values as the bit LLR values. This method requires lots of registers to save the early generated candidates. The design of this Method 1 requires 293.K gates while operating at 333 MHz. Method 2 finds the temporary minimum values of the 8 candidates generated at every clock cycle and produces the final minimum values as the as the bit LLR values after 8 clock cycles. The advantage of this design is the less required registers. The design of this Method 2 requires 181.2.K gates while operating at 1673 MHz.
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