LARGE Hardware Implementation of Bit LLR Calculation of the 256-QAM Signals in Parallel Tree Traversals for Soft-Output MIMO Detection

碩士 === 國立中正大學 === 通訊工程研究所 === 104 === In recent years, MIMO technology plays an essential role in wireless communications. In the MIMO system, detection is a very important part of the baseband receiver. As the development of hard-output detection techniques becomes mature, emphasis of current studi...

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Main Author: 陳建甫
Other Authors: LIU,TSUNG-HSIEN
Format: Others
Language:zh-TW
Published: 2016
Online Access:http://ndltd.ncl.edu.tw/handle/71457918223075897334
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spelling ndltd-TW-104CCU006500212017-05-14T04:32:07Z http://ndltd.ncl.edu.tw/handle/71457918223075897334 LARGE Hardware Implementation of Bit LLR Calculation of the 256-QAM Signals in Parallel Tree Traversals for Soft-Output MIMO Detection 多天線系統下適用256-QAM調變平行化多棵樹軟式輸出檢測器後端計算之硬體架構設計 陳建甫 碩士 國立中正大學 通訊工程研究所 104 In recent years, MIMO technology plays an essential role in wireless communications. In the MIMO system, detection is a very important part of the baseband receiver. As the development of hard-output detection techniques becomes mature, emphasis of current studies are now on developing the soft-output detection techniques to provide soft-output information to subsequent channel decoder. In this thesis, parallel multiple tree traversals for the SDM-MIMO system to generate bit LLR (Log-Likelihood Ratio) values are considered. It is known that the ORVD decomposition of the channel matrix produces R-matrix with pair-wise entries. This property is exploited in our design to produce parallel processing units in our architecture. For the 256-QAM signals and 4-by 4 antenna configuration in this thesis, a total of 64 candidates is searched by each of the 4 parallel tree traversals. Our architecture produces 8 candidates per clock cycle, indicating a total of 8 clock cycles is required to output the 64 candidates. To compute the bit LLR values, we propose two methods to find the minimum of the metrics of the 64 candidates. Method 1 waits until all the 64 candidates are output and then finds the minimum values as the bit LLR values. This method requires lots of registers to save the early generated candidates. The design of this Method 1 requires 293.K gates while operating at 333 MHz. Method 2 finds the temporary minimum values of the 8 candidates generated at every clock cycle and produces the final minimum values as the as the bit LLR values after 8 clock cycles. The advantage of this design is the less required registers. The design of this Method 2 requires 181.2.K gates while operating at 1673 MHz. LIU,TSUNG-HSIEN 劉宗憲 2016 學位論文 ; thesis 64 zh-TW
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language zh-TW
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sources NDLTD
description 碩士 === 國立中正大學 === 通訊工程研究所 === 104 === In recent years, MIMO technology plays an essential role in wireless communications. In the MIMO system, detection is a very important part of the baseband receiver. As the development of hard-output detection techniques becomes mature, emphasis of current studies are now on developing the soft-output detection techniques to provide soft-output information to subsequent channel decoder. In this thesis, parallel multiple tree traversals for the SDM-MIMO system to generate bit LLR (Log-Likelihood Ratio) values are considered. It is known that the ORVD decomposition of the channel matrix produces R-matrix with pair-wise entries. This property is exploited in our design to produce parallel processing units in our architecture. For the 256-QAM signals and 4-by 4 antenna configuration in this thesis, a total of 64 candidates is searched by each of the 4 parallel tree traversals. Our architecture produces 8 candidates per clock cycle, indicating a total of 8 clock cycles is required to output the 64 candidates. To compute the bit LLR values, we propose two methods to find the minimum of the metrics of the 64 candidates. Method 1 waits until all the 64 candidates are output and then finds the minimum values as the bit LLR values. This method requires lots of registers to save the early generated candidates. The design of this Method 1 requires 293.K gates while operating at 333 MHz. Method 2 finds the temporary minimum values of the 8 candidates generated at every clock cycle and produces the final minimum values as the as the bit LLR values after 8 clock cycles. The advantage of this design is the less required registers. The design of this Method 2 requires 181.2.K gates while operating at 1673 MHz.
author2 LIU,TSUNG-HSIEN
author_facet LIU,TSUNG-HSIEN
陳建甫
author 陳建甫
spellingShingle 陳建甫
LARGE Hardware Implementation of Bit LLR Calculation of the 256-QAM Signals in Parallel Tree Traversals for Soft-Output MIMO Detection
author_sort 陳建甫
title LARGE Hardware Implementation of Bit LLR Calculation of the 256-QAM Signals in Parallel Tree Traversals for Soft-Output MIMO Detection
title_short LARGE Hardware Implementation of Bit LLR Calculation of the 256-QAM Signals in Parallel Tree Traversals for Soft-Output MIMO Detection
title_full LARGE Hardware Implementation of Bit LLR Calculation of the 256-QAM Signals in Parallel Tree Traversals for Soft-Output MIMO Detection
title_fullStr LARGE Hardware Implementation of Bit LLR Calculation of the 256-QAM Signals in Parallel Tree Traversals for Soft-Output MIMO Detection
title_full_unstemmed LARGE Hardware Implementation of Bit LLR Calculation of the 256-QAM Signals in Parallel Tree Traversals for Soft-Output MIMO Detection
title_sort large hardware implementation of bit llr calculation of the 256-qam signals in parallel tree traversals for soft-output mimo detection
publishDate 2016
url http://ndltd.ncl.edu.tw/handle/71457918223075897334
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