| Summary: | 碩士 === 中原大學 === 機械工程研究所 === 104 === With the advancements in technology, electronics products are continuously being miniaturized, low weight and multi-functions in recent years. Generally, lithography procedures are used in the semiconductor industry to achieve the desired miniaturization but are bound by physical limits which are hard to overcome. To resolve this problem, planar 2D integration is proposed to be replaced by 3D stacking. 3D integrated circuits (3D-ICs) is expected to be more mainstream in the following years. In addition, 3D-ICs is assembled from different types of chips. The performance in the integration of different materials must be considered in product design.
To resolve and simplify the critical assembly issue regarding the interposer of 3D integrated circuits, a prototype of an embedded interposer carrier (EIC) is developed and show in this research. To complete good co-planarity of the EIC assembled by either dies or a printed circuit board, serious warpage induced during the laminating process of multi-stacked organic films needs to be resolved. Hence, a unique design with an additional ring-type stiff frame is proposed and introduced into EIC fabrication. Through process-based simulation combined with the full factor design approach, a restraint for the warping of EIC lower than 169 μm is estimated; a steel-made ring-type frame combined with suitable conjugations of laminated materials is considered. Consequently, the assembly reliability of 3D-ICs through EIC technology is expected to increase significantly.
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