The Design for A High Voltage Split Gate and Vertical Field Plate Poly-Si Thin Film Transistor

• Main Authors: Jian-Liang Chen, 陳建良
• Other Authors: 簡鳳佐
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/sauwqh

碩士 === 逢甲大學 === 電子工程學系 === 104 === Poly-Si TFTs are widely used in various fields, including AM-LCDs, 3-D integrated circuits because of their high carrier mobility and driving current for the manufacturing and applications of large-area microelectronics. The technology is a promised candidate for the ultimate goal of building fully integrated flat panel display system-on-panel (SOP) as a controller and memory. It is well known that the device high drain electric field (E) and impact ionization (IMP) can cause several undesirable effects, such as large leakage current, kink effect, and hot carrier effect in TFT. Previously studies used LDD, offset, RSD and FID structures to overcome those drawbacks. However, the devices mentioned above only focused on reducing the high drain E and had their limitation, especially on improving the device operation voltage. In this paper, we propose a project entitled “The Design for A High Voltage Split Gate and Vertical Field Plate Poly-Si Thin Film Transistor”. We combine split gate、RSD and vertical field plate (VFP) concepts to design the device structure. Based on our simulation results, the VFP can alert the current path far away from high electric field area to reduce the IMP to reduce the kink effect. In addition, the RSD structure will be beneficial to lower the drain E to reduce its nun-ideal effects. We also use N+ area in split gate structure to overcome the parasitic BJT effect to lower the kink effect. This design can increase the devices breakdown voltage better than the conventional structure. This design do not need an additional mask that conventional RSD device need. The split gate VFPTFT structure also doesn’t require very complicated processes or CMP steps.