Design and Implementation of Phase-Locked Loop With Wide Range and Low Noise forBluetooth and WLAN Operation
碩士 === 華梵大學 === 電子工程學系碩士班 === 104 === Phase Locked Loop, PLL[1-3] are widely use in cable transmission and wireless transmission, is a very important circuit, along with the technological development and advances in semiconductor process, the development of the process of making the whole circuit ar...
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ndltd-TW-104HCHT04280022019-05-15T22:17:47Z http://ndltd.ncl.edu.tw/handle/5f4yqc Design and Implementation of Phase-Locked Loop With Wide Range and Low Noise forBluetooth and WLAN Operation 應用於藍芽通訊及無線區域網路之鎖相迴路具有寬範圍低雜訊設計與實務 Chiu,Huan-Kai 邱煥凱 碩士 華梵大學 電子工程學系碩士班 104 Phase Locked Loop, PLL[1-3] are widely use in cable transmission and wireless transmission, is a very important circuit, along with the technological development and advances in semiconductor process, the development of the process of making the whole circuit area smaller and smaller, but also to join in the same area more circuits save space, increase the operating speed of the wafer. In the phase-locked loop, designers toward low power consumption, low noise, wide range, quick-lock as the main goal, which is the basic phase-locked loop to improve innovation, and thus achieve better output effect. The thesis circuit are using TSMC 0.18um 1P6M 1.8V COMS process implementation. The first chip is a phase-locked loop using a traditional PLL with multiplexer coupled to achieve multi-frequency clock generator output for Bluetooth communications applications, it’s chip area is 0.88 ∙ 0.88mm ^ 2, using a transistor number 212, maximum output frequency is 3GHz, the input reference frequency is 75MHz, the output frequency is 2.4GHz, charge pump current size of 500uA, frequency divider divisor of 32. Second chip using the traditional phase-locked loop, voltage control oscillator to change it’s architecture to achieve low noise, a wide range of applied Bluetooth and wireless LAN communications of the frequency synthesizer, the original multiband voltage controlled shock is to have a low noise, the advantages of a wide range of operations, but the voltage control oscillator output gain are all in the same direction, in the operation of the switching circuit control voltage band discontinuity, thus resulting in longer lock time, so change The output gain is a positive and negative, to shorten the lock time but also has low noise, the advantages of a wide range of operations. Chuang,Chi-Nan 莊基男 2015 學位論文 ; thesis 81 zh-TW |
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碩士 === 華梵大學 === 電子工程學系碩士班 === 104 === Phase Locked Loop, PLL[1-3] are widely use in cable transmission and wireless transmission, is a very important circuit, along with the technological development and advances in semiconductor process, the development of the process of making the whole circuit area smaller and smaller, but also to join in the same area more circuits save space, increase the operating speed of the wafer. In the phase-locked loop, designers toward low power consumption, low noise, wide range, quick-lock as the main goal, which is the basic phase-locked loop to improve innovation, and thus achieve better output effect.
The thesis circuit are using TSMC 0.18um 1P6M 1.8V COMS process implementation. The first chip is a phase-locked loop using a traditional PLL with multiplexer coupled to achieve multi-frequency clock generator output for Bluetooth communications applications, it’s chip area is 0.88 ∙ 0.88mm ^ 2, using a transistor number 212, maximum output frequency is 3GHz, the input reference frequency is 75MHz, the output frequency is 2.4GHz, charge pump current size of 500uA, frequency divider divisor of 32. Second chip using the traditional phase-locked loop, voltage control oscillator to change it’s architecture to achieve low noise, a wide range of applied Bluetooth and wireless LAN communications of the frequency synthesizer, the original multiband voltage controlled shock is to have a low noise, the advantages of a wide range of operations, but the voltage control oscillator output gain are all in the same direction, in the operation of the switching circuit control voltage band discontinuity, thus resulting in longer lock time, so change The output gain is a positive and negative, to shorten the lock time but also has low noise, the advantages of a wide range of operations.
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author2 |
Chuang,Chi-Nan |
author_facet |
Chuang,Chi-Nan Chiu,Huan-Kai 邱煥凱 |
author |
Chiu,Huan-Kai 邱煥凱 |
spellingShingle |
Chiu,Huan-Kai 邱煥凱 Design and Implementation of Phase-Locked Loop With Wide Range and Low Noise forBluetooth and WLAN Operation |
author_sort |
Chiu,Huan-Kai |
title |
Design and Implementation of Phase-Locked Loop With Wide Range and Low Noise forBluetooth and WLAN Operation |
title_short |
Design and Implementation of Phase-Locked Loop With Wide Range and Low Noise forBluetooth and WLAN Operation |
title_full |
Design and Implementation of Phase-Locked Loop With Wide Range and Low Noise forBluetooth and WLAN Operation |
title_fullStr |
Design and Implementation of Phase-Locked Loop With Wide Range and Low Noise forBluetooth and WLAN Operation |
title_full_unstemmed |
Design and Implementation of Phase-Locked Loop With Wide Range and Low Noise forBluetooth and WLAN Operation |
title_sort |
design and implementation of phase-locked loop with wide range and low noise forbluetooth and wlan operation |
publishDate |
2015 |
url |
http://ndltd.ncl.edu.tw/handle/5f4yqc |
work_keys_str_mv |
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