The Evaluation of 6T-SRAM for GAA MOSFETs and FinFETs at 7 nm and 10 nm Technology Nodes
碩士 === 國立成功大學 === 微電子工程研究所 === 104 === As the semiconductor industry continues to advance, it has encountered many physical limitations, mostly related to short-channel effects (SCEs). Below node 22, the multi-gate structure has become the solution to improve the gate controllability. In this thesis...
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ndltd-TW-104NCKU54280292019-05-15T22:54:09Z http://ndltd.ncl.edu.tw/handle/x699be The Evaluation of 6T-SRAM for GAA MOSFETs and FinFETs at 7 nm and 10 nm Technology Nodes 全包覆式閘極電晶體與鰭式電晶體組成6T靜態隨機存取記憶體的效能評估 Meng-YenWu 吳孟晏 碩士 國立成功大學 微電子工程研究所 104 As the semiconductor industry continues to advance, it has encountered many physical limitations, mostly related to short-channel effects (SCEs). Below node 22, the multi-gate structure has become the solution to improve the gate controllability. In this thesis, we benchmark 6T-SRAM of GAA MOSFETs and FinFETs and present the performance of both devices. We find that GAA MOSFETs with stacking technique provide higher drive current (per pitch) than FinFETs do. However the intrinsic delay (CV/ID) property is contrary. Static random access memory (SRAM) occupies a large portion of die size and consumes most of the standby leakages. 6T-SRAM has been designed as different configurations for high density (HD), low voltage (LV) and high performance (HP). Using a calibrated compact model, we can project the SNM and writeability of the 6T-SRAM for both devices in different configurations. And the characteristics of 6T-SRAM for all combination are demonstrated. The yield estimation is also done by the calibrated macro-model. The yield estimation and the minimum cell operation voltage (Vmin) for all design combinations of SRAM are presented in this work. By adjusting the channel width of the pass-gate devices, we optimize the GAA MOSFET SRAM in LV configuration to improve Vmin. However, this method can not be used for FinFETs. Although it suffers from the area penalty, the GAA MOSFETs show the potential for SRAM design. Wei-Chou Hsu Meng-Hsueh Chiang 許渭州 江孟學 2016 學位論文 ; thesis 44 en_US |
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碩士 === 國立成功大學 === 微電子工程研究所 === 104 === As the semiconductor industry continues to advance, it has encountered many physical limitations, mostly related to short-channel effects (SCEs). Below node 22, the multi-gate structure has become the solution to improve the gate controllability. In this thesis, we benchmark 6T-SRAM of GAA MOSFETs and FinFETs and present the performance of both devices. We find that GAA MOSFETs with stacking technique provide higher drive current (per pitch) than FinFETs do. However the intrinsic delay (CV/ID) property is contrary. Static random access memory (SRAM) occupies a large portion of die size and consumes most of the standby leakages. 6T-SRAM has been designed as different configurations for high density (HD), low voltage (LV) and high performance (HP). Using a calibrated compact model, we can project the SNM and writeability of the 6T-SRAM for both devices in different configurations. And the characteristics of 6T-SRAM for all combination are demonstrated.
The yield estimation is also done by the calibrated macro-model. The yield estimation and the minimum cell operation voltage (Vmin) for all design combinations of SRAM are presented in this work. By adjusting the channel width of the pass-gate devices, we optimize the GAA MOSFET SRAM in LV configuration to improve Vmin. However, this method can not be used for FinFETs. Although it suffers from the area penalty, the GAA MOSFETs show the potential for SRAM design.
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Wei-Chou Hsu |
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Wei-Chou Hsu Meng-YenWu 吳孟晏 |
author |
Meng-YenWu 吳孟晏 |
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Meng-YenWu 吳孟晏 The Evaluation of 6T-SRAM for GAA MOSFETs and FinFETs at 7 nm and 10 nm Technology Nodes |
author_sort |
Meng-YenWu |
title |
The Evaluation of 6T-SRAM for GAA MOSFETs and FinFETs at 7 nm and 10 nm Technology Nodes |
title_short |
The Evaluation of 6T-SRAM for GAA MOSFETs and FinFETs at 7 nm and 10 nm Technology Nodes |
title_full |
The Evaluation of 6T-SRAM for GAA MOSFETs and FinFETs at 7 nm and 10 nm Technology Nodes |
title_fullStr |
The Evaluation of 6T-SRAM for GAA MOSFETs and FinFETs at 7 nm and 10 nm Technology Nodes |
title_full_unstemmed |
The Evaluation of 6T-SRAM for GAA MOSFETs and FinFETs at 7 nm and 10 nm Technology Nodes |
title_sort |
evaluation of 6t-sram for gaa mosfets and finfets at 7 nm and 10 nm technology nodes |
publishDate |
2016 |
url |
http://ndltd.ncl.edu.tw/handle/x699be |
work_keys_str_mv |
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