| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 104 === The tradeoff between power consumption and performance of microprocessor is a major consideration issue in embedded devices with limited energy resource. Therefore, several power management technologies are proposed to reduce power consumption at runtime. These technologies require the status of power consumption at runtime to manage strategy. The techniques can be divided into two major categories, which are meter-based and counter-based, respectively. In this thesis, we focus on the domain of counter-based evaluation, which is computing power consumption based on the information of performance counters at runtime. To improve the accuracy of counter-based evaluation, several power models are proposed in last decades. Moreover, most of the previous studies consider dynamic power as the major factors in the power models. However, the static power dominates the power consumption of microprocessor while complementary metal-oxide-semiconductor (CMOS) processes improving. Furthermore, the variation of static power at runtime is intensifying since the operating temperature of microprocessor is elevating. These phenomena can result in the traditional power models is not suitable for the microprocessor produced in advanced-technology.
In this thesis, we proposed a power model which considers and evaluates dynamic and static power simultaneously. This can increase the accuracy power model while it is applied to microprocessor with advanced technology. Also, we analyze the major performance counters which can be applied to evaluate static and dynamic power, respectively.
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