28nm High-k Metal Gate 4kb SRAM-Based FIFO with Ripple Bit-Line
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === Nowadays, the embedded memory operating in low voltage progressively becomes a major trend in System-On-Chip (SoCs) to reduce the dynamic and standby power for portable devices and for ultra-low power bio-medical and wireless sensor applications. This the...
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ndltd-TW-104NCTU54281502019-05-15T23:08:41Z http://ndltd.ncl.edu.tw/handle/t7w2u7 28nm High-k Metal Gate 4kb SRAM-Based FIFO with Ripple Bit-Line 28奈米高介電係數金屬閘極4kb先進先出記憶體 劉皓軒 碩士 國立交通大學 電子工程學系 電子研究所 104 Nowadays, the embedded memory operating in low voltage progressively becomes a major trend in System-On-Chip (SoCs) to reduce the dynamic and standby power for portable devices and for ultra-low power bio-medical and wireless sensor applications. This thesis presents a novel two-port disturb-free 9T SRAM-based FIFO with ripple read bit-line (RBL) and negative write bit-line (WBL) write assist structure to enhance subthreshold operation. As the process scales down, the wire delay little by little dominates the whole delay, especially for the subthreshold region. The proposed Ripple bit-line structure divide the bit-line into several segments by the ripple buffer. Therefore, the wire delay can be reduced apparently. Furthermore, due to the programmable property of FIFO, the Ripple bit-line structure can reduce the power consumption efficiently. The proposed 9T SRAM cell has independent single-ended RBL and WBL and bit-interleaving architecture for enhanced soft error immunity. A 4kb test chip is implemented in UMC 28-nm high-k metal gate (HKMG) CMOS technology. Measured full functionality is error-free from 0.9V down to 0.4V. The measured maximum operation frequency at 0.9V , tt corner and 25℃ is 1.1GHz.. 莊景德 2016 學位論文 ; thesis 62 en_US |
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碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === Nowadays, the embedded memory operating in low voltage progressively becomes a major trend in System-On-Chip (SoCs) to reduce the dynamic and standby power for portable devices and for ultra-low power bio-medical and wireless sensor applications.
This thesis presents a novel two-port disturb-free 9T SRAM-based FIFO with ripple read bit-line (RBL) and negative write bit-line (WBL) write assist structure to enhance subthreshold operation. As the process scales down, the wire delay little by little dominates the whole delay, especially for the subthreshold region. The proposed Ripple bit-line structure divide the bit-line into several segments by the ripple buffer. Therefore, the wire delay can be reduced apparently. Furthermore, due to the programmable property of FIFO, the Ripple bit-line structure can reduce the power consumption efficiently. The proposed 9T SRAM cell has independent single-ended RBL and WBL and bit-interleaving architecture for enhanced soft error immunity. A 4kb test chip is implemented in UMC 28-nm high-k metal gate (HKMG) CMOS technology. Measured full functionality is error-free from 0.9V down to 0.4V. The measured maximum operation frequency at 0.9V , tt corner and 25℃ is 1.1GHz..
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author2 |
莊景德 |
author_facet |
莊景德 劉皓軒 |
author |
劉皓軒 |
spellingShingle |
劉皓軒 28nm High-k Metal Gate 4kb SRAM-Based FIFO with Ripple Bit-Line |
author_sort |
劉皓軒 |
title |
28nm High-k Metal Gate 4kb SRAM-Based FIFO with Ripple Bit-Line |
title_short |
28nm High-k Metal Gate 4kb SRAM-Based FIFO with Ripple Bit-Line |
title_full |
28nm High-k Metal Gate 4kb SRAM-Based FIFO with Ripple Bit-Line |
title_fullStr |
28nm High-k Metal Gate 4kb SRAM-Based FIFO with Ripple Bit-Line |
title_full_unstemmed |
28nm High-k Metal Gate 4kb SRAM-Based FIFO with Ripple Bit-Line |
title_sort |
28nm high-k metal gate 4kb sram-based fifo with ripple bit-line |
publishDate |
2016 |
url |
http://ndltd.ncl.edu.tw/handle/t7w2u7 |
work_keys_str_mv |
AT liúhàoxuān 28nmhighkmetalgate4kbsrambasedfifowithripplebitline AT liúhàoxuān 28nàimǐgāojièdiànxìshùjīnshǔzhájí4kbxiānjìnxiānchūjìyìtǐ |
_version_ |
1719140578054111232 |