| Summary: | 碩士 === 國立交通大學 === 理學院應用科技學程 === 104 === Wafer level package is one of the advanced integrated circuit (IC) packages.The packaging processing is carried out directly on the whole wafer after it is produced. Then, the packed wafer is cut into single ICs. Neither wire bonding nor fillers are required in the process. After being packaged and cutt, the chip size is very close to the original crystalline grain of the device. As a consequence, the packaging process is named as wafer level chip scale package(WLCSP), which is currently an important issue for the research and development of major packaging companies.
Here we concentrate on refining the wafer level packaging process and packaging materials analysis. The flow of process for the wafer level packaging and the processing methods are introduced in the beginning.Our experimental
methods are presented and the experimental results are summarized in short. The material analysis was carried out by using scanning electron microscope (SEM) and the sizes of silver particles were investigated. In addition, the stencil and scraper printing parameters were adjusted to improve the silver paste printing.The most importance is that the quality of silver paste printing was maintained for the paste of low concentration of silver particles. The paste printing quality was inspected by a white light interferometer. It is confirmed that the surface of
the circuit board is flat and the roughness is small enough, even though the silver paste with low concentrations (such as 70%) of silver particles is used.Moreover, the using of low concentration silver paste passed all electrical measurements and reliability tests as well.
To increase the durability of the packaging, we used under-filler with glues of different viscosity by spraying instruments for the final stage of packaging process. It is found that the under-filler coating on the surface of the wafer help to protect our ICs. The protection solves many common problems, such as damages due to the transportation of IC wafers and the surface mount device (SMT) processes.
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