| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 104 === A 0.8 ~ 8.1 GHz wide range phase-locked loop (WRPLL) with bandwidth calibration mechanism is proposed. In this thesis, triple-push technique is used to extend the oscillator tuning range without influence the stability of phase-locked loop. Furthermore, it can relieve difficulties effectively in design loop bandwidth for wide range application. For the weakness of the tripler output power, differential structure are used in oscillator and tripler to enhance 3rd harmonic energy. The output swing of tripler is about twice as large as the traditional single-ended structure. The off-chip control signals are used to adjust both divider ratio and charge pump current in order to maintain the bandwidth and stability across the operating range. In a addition, instead of using any other phase averaging techniques, this thesis proposed a highly symmetric layout method to reduce phases mismatch without increase extra area cost.
The experiment chip of the proposed WRPLL was implemented with 90 nm CMOS process. The measured output frequency is 0.8 ~ 2.7 GHz for PLL output and 2.4 ~ 8.1 GHz for tripler output at 1.0 V supply voltage with 13.9 mW power consumption at the highest operating frequency. The maximum improvement of phase noise after bandwidth calibration is 10 dBc/Hz at 1 MHz frequency offset at 2.7 GHz output frequency. The full chip area is 1.20 mm2 and the core area is 0.048 mm2.
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