| Summary: | 博士 === 國立清華大學 === 資訊工程學系 === 104 === Power consumption has become one of the primary bottlenecks to meet the Moore's law. To deal with this issue, many emerging low power technologies have been explored recently. At the design level, traditionally, we expect that circuit designs can be executed without errors. However, for error resilient applications such as image processing, 100% correctness is not necessary. By pursuing less than 100% correctness, power consumption can be significantly reduced. Recently, Probabilistic CMOS (PCMOS) and Probabilistic Boolean Circuits (PBCs) have been proposed to deal with power consumption issue.
On the other hand, at the device level, Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra low power consumption. Furthermore, a reconfigurable SET array architecture has been proposed to deal with the reliability issue. Recently, several automated mapping approaches were proposed for area minimization of reconfigurable SET arrays.
However, the automation flows for these two technologies are still not robust. For the PBC technology, no correctness analysis and power optimization algorithms were proposed. As for the SET array technology, no mapping algorithms considering the existence of defective nanowire segments were proposed. Furthermore, before the defect-aware mapping, we have to know the locations of defects in SET arrays. Therefore, in this dissertation, we propose corresponding solutions to deal with these issues.
For the part of PBC, we first propose a statistical approach for evaluating the correctness of PBCs. Then, we propose strategies for power optimization of PBCs. Finally, we integrate these strategies with the correctness analysis as a power optimization algorithm for PBCs. The experimental results show that the proposed correctness analysis method is highly efficient and accurate, and that the power optimization algorithm saves 36% of total power-delay-product on average under a correctness constraint of 90% on a set of IWLS 2005 benchmarks.
For the part of SET array, this dissertation presents the first diagnosis approach to identify the locations of defects in SET arrays followed by two defect-aware algorithms for mapping SET arrays in different scenarios. The experimental results show that the proposed diagnosis method can detect 100% of defects under a defect rate and distribution in SET arrays. As for the mapping algorithms, the results show that our approach can successfully map the SET arrays with 11.13% and 7.69% width overhead on average in the baseline detour mapping algorithm and defect-reuse mapping algorithm, respectively, in the presence of 5000 ppm defects.
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