| Summary: | 碩士 === 國立清華大學 === 電子工程研究所 === 104 === Nowadays, polar modulation transmitter is a popular research topic. In this architecture, a RF signal is separated into two parts: its amplitude and phase. The phase component is fed into a power amplifier, and the amplitude component is fed into a control circuit that modulates the supply voltage of the power amplifier accordingly. Thus in a polar modulation system, it is allowed to use a highly non-linear power amplifier such as a class-E amplifier. Compared to ordinary power amplification, this architecture favors both high linearity and power-added-efficiency. However, the recent researches on such architecture are mostly centered around 2.4 GHz.
In this thesis, a new polar modulation system at 10 GHz is proposed. It uses a multiple-output DC-DC converter to provide several different regulated voltages to the power amplifier. An ADC is needed to sense the envelope of the signal in order to select the voltage that is applied to the power amplifier accordingly. This technique improves the efficiency of the power amplifier in different power levels. In this thesis, a 10 GHz class-E power amplifier prototype and a multiple-output DC-DC converter are demonstrated in CMOS 90-nm technology.
The implemented class-E power amplifier reaches an output power of 11.7 dBm, an output 1-dB compression point of 10.32 dBm, and a power-added-efficiency of 40.36% with a supply voltage of 1.5 V.
The multiple-output DC-DC converter is a multiple outputs low dropout regulator that provides three distinct outputs from 0.7 V to 0.85 V. These voltages are used to change the supply voltage of the class-E power amplifier for efficiency enhancement.
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