Improved Electrical Characteristics of Large-Sized Amorphous Silicon Thin-Film Transistors for Liquid Crystal Display

• Main Authors: Lee, Hao Chieh, 李豪捷
• Other Authors: Chang-Liao, Kuei-Shu
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/yc4amm

博士 === 國立清華大學 === 工程與系統科學系 === 104 === Amorphous silicon thin-film transistor (a-Si TFT) is the mainstream technique for active-matrix liquid crystal display (AMLCD), due to a good uniformity over large-area substrates, low process temperature, and a high production yield. In recent years, for cost-reduction consideration, using medium- and large-sized a-Si TFTs to form the gate driver circuits integrated on array glass substrate has attracted a lot of attention in display application. The lifetime and performance of integrated gate driver on array substrate (GOA) are dominated by the electrical characteristics of large-sized a-Si TFTs, such as threshold voltage shift (△Vth) under a long-term operation. In this thesis, to improve the electrical characteristics of large-sized a-Si TFTs, we extensively studied the process improvements and evaluated the influences of these processes on the electrical performance of devices. In addition, the channel width of large-sized a-Si TFTs studied in this thesis is ranged from 1000 to 10000 µm for being comparable to practical devices used in GOA. At first, an optimal process integration on GI and intrinsic a-Si layer of large-sized a-Si TFTs was applied and investigated. Different channel widths were designed to discuss the effect of sample size. Based on the experimental results, it was observed that the initial electrical characteristics of large-sized a-Si TFT were not influenced by optimal process integration, such as current-voltage characteristics. The off current (Ioff) of devices at different temperatures were measured as well. It was found that Ioff of large-sized a-Si TFTs could be remarkably reduced by optimal process integration, since the activation energy (Ea) of Ioff was increased. In addition, the DC stresses with high and low electrical fields were applied on the gate electrode of devices to study the instability influenced by the application of optimal integration. It was experimentally found that △Vth of large-sized a-Si TFTs could be effectively reduced by optimal process integration. In addition, the defect generation in a-Si layer was the dominated mechanism for the △Vth of devices under high and low electrical-field stresses. In the second part, to achieve further enhancements of electrical characteristics for large-sized a-Si TFTs, a front-channel treatment (FCT) with hydrogen gas on GI layer prior to the deposition of intrinsic a-Si layer and a back-channel treatment (BCT) with hydrogen gas after the deposition of intrinsic a-Si layer were applied and investigated, respectively. However, based on our experimental results, it was found that the △Vth of devices was more by the FCT, since the dominated mechanism of △Vth was defect generation in a-Si layer, which would not be reduced by the FCT on GI layer. In addition, from the observation of our data, the FCT on GI layer might cause damage to the surface of channel for devices, leading to a worse stability, instead of reducing the △Vth of devices. Besides, by applying BCT and optimizing the process time, it was observed that Ioff and △Vth of large-sized a-Si TFTs after high and low electrical-field stresses were remarkably decreased. For the experimental results of Ioff, it was found that a shorter or a longer BCT process time for devices were unsuitable for reducing the Ioff of devices. As for the results of △Vth, the dominated mechanism responsible for △Vth of devices after a high electrical-field stress was defect generation in a-Si layer rather than charge trapping in GI layer, which is different from previous studies. The difference may be caused by the different GI quality of devices, not the sample size.