Study of Vertically Stacked Poly-Si Nanosheet Field-Effect-Transistor

• Main Authors: Chang, Yu Shuo, 張佑碩
• Other Authors: Wu, Yung Chun
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/38303284729222024224

碩士 === 國立清華大學 === 工程與系統科學系 === 104 === The market demand for portable electrical equipments increase dramatically year by year., emphasizing on multifunctional, small size, light weight, etc. Under keen mutual competition environment of economic market and electronic industries, it has triggered electronic industries to improve their products to develop toward low cost, high density and scale down to react to the rapid demand in the market. Nevertheless, the expectation of scaling transistors suffered more and more difficult to design, whether the short channel effect in devices or the challenge of fabrication process are very vital research topics. In this thesis, we successfully demonstrate the stacked nanosheert(NS) vertically inversion-mode field-effect-transistors(VM-FET) in 3D stacked integrated circuit (IC) applications to increase transistor density for continuing Moore’s law. It may offer valuable information with regard to their practical industry and academic applications. This research which focus on is showing the following: (1) device process, (2).basic device characteristics analysis, (3) device simulation. In the fabrication process, we adopt the oxidation trimming method to form thin active layer and exhibit quasi-crystal channel due to the reduction of grain boundaries and defects. It is beneficial for excellent electrical performance. In the basic device characteristics analysis. First part will show the comparison of stacked NS VM-FET and conventional NS IM-FET. The stacked structure exhibits the better characteristics owing to due to the parallel resistance, resulting in smaller total resistance and improved around 4.36 times current drivability and higher ON/OFF current ratio up to 108. The 3D stacked layer can increase on-state current and maintain low leakage current. Second part will discuss about the change of width dimension for I-V characteristics with stacked structure. However, in the device simulation, we use Sentaurus TCAD to analyze and confirm the measured basic electrical characteristics As a result, we proposed the stacked NS VM-FET has better electrical characteristics. Additionally, it may offer a possible next-generation CMOS device solution and be applied in advanced system-on-chip and 3D stacked IC applications.