Study of Vertically Stacked Poly-Si Nanosheet Field-Effect-Transistor
碩士 === 國立清華大學 === 工程與系統科學系 === 104 === The market demand for portable electrical equipments increase dramatically year by year., emphasizing on multifunctional, small size, light weight, etc. Under keen mutual competition environment of economic market and electronic industries, it has triggered ele...
Main Authors: | Chang, Yu Shuo, 張佑碩 |
---|---|
Other Authors: | Wu, Yung Chun |
Format: | Others |
Language: | en_US |
Published: |
2016
|
Online Access: | http://ndltd.ncl.edu.tw/handle/38303284729222024224 |
Similar Items
-
Investigation on Vertically Stacked Gate-All-Around Nanosheet Poly-Si Junctionless CMOS Transistors
by: Chang, Chih-Yao, et al.
Published: (2018) -
Study of Vertically Stacked Nanosheet With Multi- Gate Field-Effect-Transistors
by: Yang, Yi-Yun, et al.
Published: (2017) -
Vertically Stacked Nanosheet Junctionless With Gate All Around Field-Effect-Transistors
by: Peng, Kang-Hui, et al.
Published: (2018) -
Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors
by: Meng-Ju Tsai, et al.
Published: (2019-01-01) -
Study of the Stacked Nanosheet Channels with Junctionless Field Effect Transistor
by: HSU,YA-TING, et al.
Published: (2019)