Design of 60 GHz Bidirectional Beamformer and Switchless Bidirectional Amplifier

• Main Authors: Kuang-Sheng Yeh, 葉光聖
• Other Authors: 王暉
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/23445514214975232448

碩士 === 國立臺灣大學 === 電信工程學研究所 === 104 === The research topics of this thesis are switchless bidirectional amplifier (BDA) and its application in the bidirectional beamforming system. First, the advantages of bidirectional system in the communication are illustrated. In the bidirectional system, the most critical component is the BDA. Conventional BDAs are realized by two unidirectional amplifiers with switches. However, the switches produce extra loss and occupy large chip area. This thesis presents two switchless BDAs and a beamformer which built by the BDAs. By using the switchless topology, the loss and the chip size are minimized. The first BDA is realized in 90-nm CMOS process. From 57 to 66 GHz, in receiving mode, the gain is above 18.2 dB and the noise figure is below 8 dB, with 15.3 mW power consumption. In transmitting mode, the linear gain is above 13.5 dB with 46 mW power consumption. At 60 GHz, output 1 dB compression point (OP1dB) is 3.6 dBm, saturation output power (Psat) is 6.5 dBm with peak PAE of 7.3%. The chip size is 0.44 mm square. The second BDA is realized in 40-nm low power CMOS process, with the transformer-coupled matching network and neutralization technique. From 52 to 62 GHz, in receiving mode, the gain is above 10.1 dB and the noise figure (NF) is below 8 dB, with 22.3 mW power consumption. In transmitting mode, the linear gain is above 13.4 dB, with 49.5 mW power consumption. At 55 GHz, the output 1 dB compression point (OP1dB) is 2.7 dBm, saturation output power (Psat) is 9.7 dBm with peak PAE of 8.5%. The chip size is 0.21 mm square. Comparing with the first BDA, the chip size is reduced due to elimination of bypass capacitors in differential topology, and compact transformers as the matching networks. In addition, the output power and PAE are enhanced by using the differential power combining. Comparing with published works, the two BDAs are the first switchless BDA realized on Si-based process for 60 GHz application, and the 40-nm BDA demonstrate the minimum chip size. By using the 40-nm BDA, a bidirectional beamformer which applied in the high speed communication of the mobile devices is designed. Incorporated with four separated 4-element (4×4) antenna arrays, the beamformer supports 16-beam directions. By using the bidirectional architecture, all the passive components and I/O are shared in the transmitting and the receiving paths to minimize the chip size. Moreover, due to the compact size of the BDAs, the system chip is compact as 2.9 mm square. With the CMOS process and the minimized circuit size in the large-scale phased array, the reliability issue in high I/O connected package and heterogeneous integration can be solved.