The Algorithm and VLSI Architecture of a High-Throughput Motion Estimation with Adaptive Search Range for HEVC Systems

• Main Authors: Tzu-Ting Liao, 廖紫廷
• Other Authors: Chung-An Shen
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/99197437509698135639

碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === This thesis presents the VLSI architecture and an efficient algorithm of a high-throughput Motion Estimation (ME) for High Efficiency Video Coding (HEVC) systems. In order to support Ultra High-Definition videos, the system throughput is increased by proposed adaptive search range Algorithm that can reduce the computational complexity while performing Sum of Absolute Difference (SAD) circuits. The variable block sizes within a CTU perform ME in a shared search window and the size of search range is estimated by the MVP of LCU and is inherently adaptive to the characteristic of the video content. Specifically, in the proposed approach, the search window is enlarged for fast motion video and will be shrunk for slow motion video. The statistical results show that the average search candidates of the proposed search range is 160 for a CTU. This leads to 96.2% reduction of search candidates with only 0.05 dB drop in average peak signal-to-noise ratio (PSNR) [25] compared to the conventional 32 full-search example. The proposed design is based on TSMC 90nm technology and the pre-layout area complexity is 274.5 KGE and the memory usage is 8 KB. With co-design of algorithm and architecture, the proposed design can achieve resolution of 4096×2160 with 60 frames per second (fps) under 211 MHz. Comparing to the related works, the proposed design can achieve the highest hardware-efficiency.