High-Speed Baseband OFDM System Design
碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === The thesis is a design of baseband circuits system to enhance the throughput of OFDM. In IEEE 802.11a protocol, it leaves space between each circuit to avoid signal interference issues, which costs FFT five-times more of the symbol time to process OFDM symbol. I...
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ndltd-TW-104NTUS54281072017-09-24T04:40:50Z http://ndltd.ncl.edu.tw/handle/34492168540359678455 High-Speed Baseband OFDM System Design 高速OFDM系統之基頻電路設計 Tzu-Yu Weng 翁子育 碩士 國立臺灣科技大學 電子工程系 104 The thesis is a design of baseband circuits system to enhance the throughput of OFDM. In IEEE 802.11a protocol, it leaves space between each circuit to avoid signal interference issues, which costs FFT five-times more of the symbol time to process OFDM symbol. In order to enhance the throughput, we use 5 stage of the instruction pipeline as our overall structure of the design. The instruction pipeline of FFT can process multiple signals in the same time. We are able to shorten spare time until it reaches zero. The speed of transmitter and receiver are ten times faster than original speed. The Packet format is based on IEEE 802.11 with the insertion of IEEE 802.16 subcarrier and pilot to maximize bandwidth. Time series is adjusted based upon the highest speed that Virtex 6 baseband circuits are able to endure. Hardware is designed accordingly with the original architect of IEEE 802.11 protocol and packet format. Baseband design contains packet length calculation, cyclic redundancy code calculation, time control, short training symbol, long training symbol, and signal frame. Huan-Chun Wang 王煥宗 2016 學位論文 ; thesis 55 zh-TW |
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碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === The thesis is a design of baseband circuits system to enhance the throughput of OFDM. In IEEE 802.11a protocol, it leaves space between each circuit to avoid signal interference issues, which costs FFT five-times more of the symbol time to process OFDM symbol. In order to enhance the throughput, we use 5 stage of the instruction pipeline as our overall structure of the design. The instruction pipeline of FFT can process multiple signals in the same time. We are able to shorten spare time until it reaches zero. The speed of transmitter and receiver are ten times faster than original speed. The Packet format is based on IEEE 802.11 with the insertion of IEEE 802.16 subcarrier and pilot to maximize bandwidth. Time series is adjusted based upon the highest speed that Virtex 6 baseband circuits are able to endure. Hardware is designed accordingly with the original architect of IEEE 802.11 protocol and packet format. Baseband design contains packet length calculation, cyclic redundancy code calculation, time control, short training symbol, long training symbol, and signal frame.
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author2 |
Huan-Chun Wang |
author_facet |
Huan-Chun Wang Tzu-Yu Weng 翁子育 |
author |
Tzu-Yu Weng 翁子育 |
spellingShingle |
Tzu-Yu Weng 翁子育 High-Speed Baseband OFDM System Design |
author_sort |
Tzu-Yu Weng |
title |
High-Speed Baseband OFDM System Design |
title_short |
High-Speed Baseband OFDM System Design |
title_full |
High-Speed Baseband OFDM System Design |
title_fullStr |
High-Speed Baseband OFDM System Design |
title_full_unstemmed |
High-Speed Baseband OFDM System Design |
title_sort |
high-speed baseband ofdm system design |
publishDate |
2016 |
url |
http://ndltd.ncl.edu.tw/handle/34492168540359678455 |
work_keys_str_mv |
AT tzuyuweng highspeedbasebandofdmsystemdesign AT wēngziyù highspeedbasebandofdmsystemdesign AT tzuyuweng gāosùofdmxìtǒngzhījīpíndiànlùshèjì AT wēngziyù gāosùofdmxìtǒngzhījīpíndiànlùshèjì |
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