Low Power Wide-Locking Range Divide-by-2 Injection-Locked Frequency Divider and Small Die Area Capacitive Cross-coupled Injection-Locked Frequency Divider

碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === Firstly, this thesis presents a new divide-by-2 ILFD, which is implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 capacitive cross-coupled ILFD has wide locking range at low power consumption by lowering the gate bias of the capacitive cross-coup...

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Main Authors: Meng-Yan Fang, 方孟彥
Other Authors: Sheng-Lyang Jang
Format: Others
Language:en_US
Published: 2016
Online Access:http://ndltd.ncl.edu.tw/handle/61603386094193222681
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spelling ndltd-TW-104NTUS54281552017-09-24T04:40:50Z http://ndltd.ncl.edu.tw/handle/61603386094193222681 Low Power Wide-Locking Range Divide-by-2 Injection-Locked Frequency Divider and Small Die Area Capacitive Cross-coupled Injection-Locked Frequency Divider 低功耗寬鎖頻範圍注入鎖定除二除頻器及小型電容耦合注入鎖定除二除頻器 Meng-Yan Fang 方孟彥 碩士 國立臺灣科技大學 電子工程系 104 Firstly, this thesis presents a new divide-by-2 ILFD, which is implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 capacitive cross-coupled ILFD has wide locking range at low power consumption by lowering the gate bias of the capacitive cross-coupled transistor. At the drain-source bias of 0.4V and at the incident power of 0 dBm, the locking range is 3.6 GHz (36.28%) from 7.2 to 10.8GHz at the power consumption of 1.52mW. The die area is 1.2 ×0.951 mm2. The second circuit is a wide locking range divide-by-3 LC injection-locked frequency divider (ILFD) in the TSMC 0.18 μm SiGe BiCMOS process. The divide-by-3 ILFD uses a cross-coupled NMOS pair, an injection MOSFET pair and a 6th order RLC resonator. The divide-by-3 ILFD has two oscillation frequency bands. The ILFD-core power consumption is 6.318 mW. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm, a wide locking range 6.2GHz (65.26%) from 6.4 to 12.6 GHz is obtained by over-lapping the locking ranges at a fixed bias condition. The die area is 1.1×0.84 mm2. Finally, a lower power and wide locking range divide-by-2 capacitive cross-coupled injection-locked frequency divider (ILFD) is implemented in the TSMC standard 0.18 μm CMOS process. The ILFD is based on a capacitive cross-coupled VCO with one injection MOSFET for coupling the external signal to the resonator. The ILFD uses one 3-dimensional inductor to reduce the die area. At the supply voltage of 1V, the divider’s free-running frequency is 2.27 GHz, and at the incident power of 0 dBm the locking range is about 5.9GHz (132.58%) from 1.5GHz to 7.4 GHz. The core power consumption is 10.22mW. At low power mode, the ILFD has higher figure of merit. The die area is 0.719×0.637 mm2. Sheng-Lyang Jang Miin-Horng Juang 張勝良 莊敏宏 2016 學位論文 ; thesis 114 en_US
collection NDLTD
language en_US
format Others
sources NDLTD
description 碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === Firstly, this thesis presents a new divide-by-2 ILFD, which is implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 capacitive cross-coupled ILFD has wide locking range at low power consumption by lowering the gate bias of the capacitive cross-coupled transistor. At the drain-source bias of 0.4V and at the incident power of 0 dBm, the locking range is 3.6 GHz (36.28%) from 7.2 to 10.8GHz at the power consumption of 1.52mW. The die area is 1.2 ×0.951 mm2. The second circuit is a wide locking range divide-by-3 LC injection-locked frequency divider (ILFD) in the TSMC 0.18 μm SiGe BiCMOS process. The divide-by-3 ILFD uses a cross-coupled NMOS pair, an injection MOSFET pair and a 6th order RLC resonator. The divide-by-3 ILFD has two oscillation frequency bands. The ILFD-core power consumption is 6.318 mW. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm, a wide locking range 6.2GHz (65.26%) from 6.4 to 12.6 GHz is obtained by over-lapping the locking ranges at a fixed bias condition. The die area is 1.1×0.84 mm2. Finally, a lower power and wide locking range divide-by-2 capacitive cross-coupled injection-locked frequency divider (ILFD) is implemented in the TSMC standard 0.18 μm CMOS process. The ILFD is based on a capacitive cross-coupled VCO with one injection MOSFET for coupling the external signal to the resonator. The ILFD uses one 3-dimensional inductor to reduce the die area. At the supply voltage of 1V, the divider’s free-running frequency is 2.27 GHz, and at the incident power of 0 dBm the locking range is about 5.9GHz (132.58%) from 1.5GHz to 7.4 GHz. The core power consumption is 10.22mW. At low power mode, the ILFD has higher figure of merit. The die area is 0.719×0.637 mm2.
author2 Sheng-Lyang Jang
author_facet Sheng-Lyang Jang
Meng-Yan Fang
方孟彥
author Meng-Yan Fang
方孟彥
spellingShingle Meng-Yan Fang
方孟彥
Low Power Wide-Locking Range Divide-by-2 Injection-Locked Frequency Divider and Small Die Area Capacitive Cross-coupled Injection-Locked Frequency Divider
author_sort Meng-Yan Fang
title Low Power Wide-Locking Range Divide-by-2 Injection-Locked Frequency Divider and Small Die Area Capacitive Cross-coupled Injection-Locked Frequency Divider
title_short Low Power Wide-Locking Range Divide-by-2 Injection-Locked Frequency Divider and Small Die Area Capacitive Cross-coupled Injection-Locked Frequency Divider
title_full Low Power Wide-Locking Range Divide-by-2 Injection-Locked Frequency Divider and Small Die Area Capacitive Cross-coupled Injection-Locked Frequency Divider
title_fullStr Low Power Wide-Locking Range Divide-by-2 Injection-Locked Frequency Divider and Small Die Area Capacitive Cross-coupled Injection-Locked Frequency Divider
title_full_unstemmed Low Power Wide-Locking Range Divide-by-2 Injection-Locked Frequency Divider and Small Die Area Capacitive Cross-coupled Injection-Locked Frequency Divider
title_sort low power wide-locking range divide-by-2 injection-locked frequency divider and small die area capacitive cross-coupled injection-locked frequency divider
publishDate 2016
url http://ndltd.ncl.edu.tw/handle/61603386094193222681
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