Dual Band Injection Lock Frequency Divider and Study of Concurrent Oscillator

碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === In wireless communication system, frequency synthesizers are used to implement the frequency up/down converting of signal. In a frequency synthesizer, voltage-controlled oscillator (VCO) and divider are the key blocks. For VCOs, low phase-noise output is require...

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Bibliographic Details
Main Authors: Cheng-Lin Li, 李承霖
Other Authors: Sheng–Lyang Jang
Format: Others
Language:en_US
Published: 2016
Online Access:http://ndltd.ncl.edu.tw/handle/52510554669465819647
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Summary:碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === In wireless communication system, frequency synthesizers are used to implement the frequency up/down converting of signal. In a frequency synthesizer, voltage-controlled oscillator (VCO) and divider are the key blocks. For VCOs, low phase-noise output is required to avoid corrupting the mixer-converted signal by close interfering tones. The output of the VCO is divided down by the frequency divider which requires operating at high frequencies, wide operating range and lower power consumption. In chapter 4, we present a wide locking range divide by four injection lock frequency divider using five on chip inductors. The ILFD using a cross coupled voltage-controlled oscillator (VCO) with one direct injection MOSFET. The resonator using five on chip inductors. The chip was implemented in the tsmc 0.18 μm SiGe 3P6M BiCMOS process. The die area is 0.865 ×0.872 mm2. The dc gate bias of cross coupled FETs can be tuned for the tradeoff between locking range and power consumption. The core power consumption is 10.34 mW at supply voltage 1.1 V. At the incident power of 0 dBm the locking range is 4.7 GHz (38.68%) from 9.8 to 14.5 GHz. In chapter 5, we present a voltage controlled concurrent oscillator. The chip was implemented in the tsmc 0.18 lm SiGe 3P6M BiCMOS process. The die area is 1.057 ×1.071 mm2. The concurrent oscillator using two VCOs coupled by an LC network. The VCO uses two units of right-handed (RH) LC resonator stacked in series, and the LC resonator is in shunt with a pair of cross-coupled transistors to compensate the loss of LC resonator. The supply voltage is 0.8 V. The high band oscillation frequency is 3.79 GHz and the power consumption is 3.43 mW. The phase noise at 1MHz frequency offset is -121.04 dBc/Hz, and FOM is -187.1 dBc/Hz. The low band oscillation frequency is 6.03 GHz and the power consumption is 1.63 mW. The phase noise at 1MHz frequency offset is -116.99 dBc/Hz, and FOM is -190.2 dBc/Hz. In chapter 6, we present a concurrent oscillator with switching mode. The oscillator consists of two cross-coupled BiCMOS oscillators with shared series-tuned LC-tank. The series-tuned LC-tank plays the role in the oscillation frequency. By varying the tail transistor the concurrent oscillation occurs. The power consumption is 2.6 mW at supply voltage 0.7 V. The chip was implemented in the tsmc 0.18 lm SiGe 3P6M BiCMOS process. The die area is 1.04 ×0.55 mm2.