An Adaptive On-Time-Controlled Buck Converter Using Frequency-Locked Techniques

碩士 === 國立臺北科技大學 === 電子工程系研究所 === 104 === Conservative ripple-based regulator possesses the advantage of fast transient response. Nevertheless, when input and output voltage are changed, it suffers the variation of switching frequency. The thesis presents an adaptive on-time (AOT) switching converte...

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Main Authors: Chia-Hao Chang, 張家豪
Other Authors: Yuh-Shyan Hwang
Format: Others
Language:zh-TW
Online Access:http://ndltd.ncl.edu.tw/handle/u3y5ze
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spelling ndltd-TW-104TIT054270932019-05-15T22:54:24Z http://ndltd.ncl.edu.tw/handle/u3y5ze An Adaptive On-Time-Controlled Buck Converter Using Frequency-Locked Techniques 使用鎖頻技術之可適應性導通時間控制的降壓轉換器 Chia-Hao Chang 張家豪 碩士 國立臺北科技大學 電子工程系研究所 104 Conservative ripple-based regulator possesses the advantage of fast transient response. Nevertheless, when input and output voltage are changed, it suffers the variation of switching frequency. The thesis presents an adaptive on-time (AOT) switching converter using frequency-locked techniques. To achieve fixed frequency, phase-locked loop (PLL) is employed to keep the switching frequency (Fsw) constant at 1MHz. The chip is fabricated in TSMC 0.35um 2P4M process. The input voltage is 3.0V, and the output voltage range is 1.2~1.8V. The simulation results show that the maximum efficiency is 94.77% when the load current is 200mA and output voltage is 1.8V. The load transient response time is about 4.914 µs and 2.826 µs when the load current changes from 120 mA to 580 mA and from 580 mA to 120 mA, respectively. Yuh-Shyan Hwang Jiann-Jong Chen 黃育賢 陳建中 學位論文 ; thesis 0 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立臺北科技大學 === 電子工程系研究所 === 104 === Conservative ripple-based regulator possesses the advantage of fast transient response. Nevertheless, when input and output voltage are changed, it suffers the variation of switching frequency. The thesis presents an adaptive on-time (AOT) switching converter using frequency-locked techniques. To achieve fixed frequency, phase-locked loop (PLL) is employed to keep the switching frequency (Fsw) constant at 1MHz. The chip is fabricated in TSMC 0.35um 2P4M process. The input voltage is 3.0V, and the output voltage range is 1.2~1.8V. The simulation results show that the maximum efficiency is 94.77% when the load current is 200mA and output voltage is 1.8V. The load transient response time is about 4.914 µs and 2.826 µs when the load current changes from 120 mA to 580 mA and from 580 mA to 120 mA, respectively.
author2 Yuh-Shyan Hwang
author_facet Yuh-Shyan Hwang
Chia-Hao Chang
張家豪
author Chia-Hao Chang
張家豪
spellingShingle Chia-Hao Chang
張家豪
An Adaptive On-Time-Controlled Buck Converter Using Frequency-Locked Techniques
author_sort Chia-Hao Chang
title An Adaptive On-Time-Controlled Buck Converter Using Frequency-Locked Techniques
title_short An Adaptive On-Time-Controlled Buck Converter Using Frequency-Locked Techniques
title_full An Adaptive On-Time-Controlled Buck Converter Using Frequency-Locked Techniques
title_fullStr An Adaptive On-Time-Controlled Buck Converter Using Frequency-Locked Techniques
title_full_unstemmed An Adaptive On-Time-Controlled Buck Converter Using Frequency-Locked Techniques
title_sort adaptive on-time-controlled buck converter using frequency-locked techniques
url http://ndltd.ncl.edu.tw/handle/u3y5ze
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