Design and Implementation of Burst-Mode Clock and Data Recovery Circuit
碩士 === 國立雲林科技大學 === 電機工程系 === 104 === Due to the requirement of the high-speed internet market, the advantage of passive optical network (PON) with high bandwidth and elimination of power supply in the optical distribution network lead to the future development. PON architecture is based on point-...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/61987510792904815191 |
| Summary: | 碩士 === 國立雲林科技大學 === 電機工程系 === 104 === Due to the requirement of the high-speed internet market, the advantage of passive optical network (PON) with high bandwidth and elimination of power supply in the optical distribution network lead to the future development. PON architecture is based on point-to-multipoint whereas the data transmission in the upstream direction may suffer from amplitude variation and phase deviation. Therefore, burst-mode clock and data recovery (CDR) is designed to achieve the characteristic of fast acquisition in order to overcome these issue.
In this thesis, two burst-mode clock and data recovery circuits are designed and implemented in TSMC 0.18μm 1P6M CMOS process. The first chip is the dual bit-rate burst-mode CDR using current mode logic. The architecture of decision circuit enables itself to operate in both 5 Gbps and 2.5 Gbps without an external control signal while the same 2.5 GHz clock is responsible to recover data. The control voltage of the voltage control oscillator for recovery clock generation is provided by phase-locked loop operated in a lower frequency. In 5 Gbps operation, data are retimed at the positive and negative edges of the recovered clocks which CDR operates at a half rate while CDR utilizes positive edges at a full rate of 2.5 Gbps. The second chip is a reference-less mixed-signal burst-mode CDR for the purpose of low power design in the developing trend of modern technology. The specification of the proposed full-rate CDR is 1.25 Gbps. The time-to-digital converter (TDC) is employed to detect the data rate for the generation of the recovered clocks from the realigning oscillator. The mixed-signal delay line inside the realigning oscillator is designed in both digital and analog types. The digital type can provide fast acquisition of clock frequency with aid of TDC while the analog type is dedicated to minimize the clock frequency deviation for better jitter performance.
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