| Summary: | 碩士 === 元智大學 === 通訊工程學系 === 104 === This thesis presents an RF front-end transmitter design in TSMC CMOS 0.18 μm technology for Long Term Evolution communication system applications. The transmitter utilizes one-step up-converter architecture to apply in usual LTE band, with total loss in 7 dB and -10.5 dBm in output third-order intercept point. The overall power consumption is about 10.2 mW. In the circuit designs, the up-convert mixer uses a double-balance operation similar to Gilbert-cell structure. The buffer is in the common source and common drain amplifier, together with parallel configuration, in a fully differential architecture. The first stage is a passive double-balance mixer, where the mixer works at the triode region, and as a resistor which was controlled by Gate’s voltage, as a double-balance structure, it could filter the noise and just need low LO signal. The second stage is a buffer which attached to the mixer to combine and gain the RF signal strength, in the situation of same output impedance; it could define larger magnitude of voltage gain. Finally, this thesis will discuss the improvement directions in the future based on the current measured results.
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