CMOS RF Direct IQ Modulator Design for LTE Applications
碩士 === 元智大學 === 通訊工程學系 === 104 === This thesis presents an RF front-end transmitter design in TSMC CMOS 0.18 μm technology for Long Term Evolution communication system applications. The transmitter utilizes one-step up-converter architecture to apply in usual LTE band, with total loss in 7 dB and -1...
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ndltd-TW-104YZU056500112017-10-15T04:36:57Z http://ndltd.ncl.edu.tw/handle/04394272043271930215 CMOS RF Direct IQ Modulator Design for LTE Applications 應用於長期演進技術之CMOS直接昇頻調變器電路研製 Yen-Chun Wen 溫彥俊 碩士 元智大學 通訊工程學系 104 This thesis presents an RF front-end transmitter design in TSMC CMOS 0.18 μm technology for Long Term Evolution communication system applications. The transmitter utilizes one-step up-converter architecture to apply in usual LTE band, with total loss in 7 dB and -10.5 dBm in output third-order intercept point. The overall power consumption is about 10.2 mW. In the circuit designs, the up-convert mixer uses a double-balance operation similar to Gilbert-cell structure. The buffer is in the common source and common drain amplifier, together with parallel configuration, in a fully differential architecture. The first stage is a passive double-balance mixer, where the mixer works at the triode region, and as a resistor which was controlled by Gate’s voltage, as a double-balance structure, it could filter the noise and just need low LO signal. The second stage is a buffer which attached to the mixer to combine and gain the RF signal strength, in the situation of same output impedance; it could define larger magnitude of voltage gain. Finally, this thesis will discuss the improvement directions in the future based on the current measured results. Chien-Chang Huang 黃建彰 2016 學位論文 ; thesis 62 zh-TW |
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碩士 === 元智大學 === 通訊工程學系 === 104 === This thesis presents an RF front-end transmitter design in TSMC CMOS 0.18 μm technology for Long Term Evolution communication system applications. The transmitter utilizes one-step up-converter architecture to apply in usual LTE band, with total loss in 7 dB and -10.5 dBm in output third-order intercept point. The overall power consumption is about 10.2 mW. In the circuit designs, the up-convert mixer uses a double-balance operation similar to Gilbert-cell structure. The buffer is in the common source and common drain amplifier, together with parallel configuration, in a fully differential architecture. The first stage is a passive double-balance mixer, where the mixer works at the triode region, and as a resistor which was controlled by Gate’s voltage, as a double-balance structure, it could filter the noise and just need low LO signal. The second stage is a buffer which attached to the mixer to combine and gain the RF signal strength, in the situation of same output impedance; it could define larger magnitude of voltage gain. Finally, this thesis will discuss the improvement directions in the future based on the current measured results.
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author2 |
Chien-Chang Huang |
author_facet |
Chien-Chang Huang Yen-Chun Wen 溫彥俊 |
author |
Yen-Chun Wen 溫彥俊 |
spellingShingle |
Yen-Chun Wen 溫彥俊 CMOS RF Direct IQ Modulator Design for LTE Applications |
author_sort |
Yen-Chun Wen |
title |
CMOS RF Direct IQ Modulator Design for LTE Applications |
title_short |
CMOS RF Direct IQ Modulator Design for LTE Applications |
title_full |
CMOS RF Direct IQ Modulator Design for LTE Applications |
title_fullStr |
CMOS RF Direct IQ Modulator Design for LTE Applications |
title_full_unstemmed |
CMOS RF Direct IQ Modulator Design for LTE Applications |
title_sort |
cmos rf direct iq modulator design for lte applications |
publishDate |
2016 |
url |
http://ndltd.ncl.edu.tw/handle/04394272043271930215 |
work_keys_str_mv |
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