SNM-Aware Subthreshold SRAM Cell and Array Designs

• Main Authors: WENG, WEI-JIA, 翁偉嘉
• Other Authors: WANG, JINN-SHYAN
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/dy79w7

碩士 === 國立中正大學 === 電機工程研究所 === 105 === In recent years, with the development of portable electronic products, all kinds of hardware are designed for low-power consumption. SRAM, it’s very important part in SOC. This paper will introduce from the point of view of cell structure to realize the importance of SRAM in sub-threshold voltage region. And then, for low-power consumption and small-area designs in 40nm process, we will discuss all the design issues about sub-threshold voltage design. First, we will list the problem of conventional 6T SRAM about sub-threshold voltage design in 40nm process, Then select the two works to meet all the sub-threshold voltage design issues. To determine the best cell size by improvement of cell design flow and the more advantageous one will be implement the complete memory circuit and improve in 40nm process. To compare advantages of each work , the another work will reference the data of the paper. Finally, we will analyze the data fully and make a conclusion.