Design Performance Enhancement Mechanisms for the On-Chip Network of the Multicore Architecture

碩士 === 中原大學 === 資訊工程研究所 === 105 === The evaluation of technology makes the modern computer architecture consist of many processing cores. The mechanism of increasing core numbers of the computer system become the major orientation of design computer systems. As the number of processing cores are inc...

Full description

Bibliographic Details
Main Authors: Teng-Yao Hsu, 許藤耀
Other Authors: Slo-Li Chu
Format: Others
Language:zh-TW
Published: 2017
Online Access:http://ndltd.ncl.edu.tw/handle/xxwjf2
id ndltd-TW-105CYCU5392028
record_format oai_dc
spelling ndltd-TW-105CYCU53920282019-05-15T23:39:16Z http://ndltd.ncl.edu.tw/handle/xxwjf2 Design Performance Enhancement Mechanisms for the On-Chip Network of the Multicore Architecture 設計適用於多核心架構之晶片互連網路效能改善機制 Teng-Yao Hsu 許藤耀 碩士 中原大學 資訊工程研究所 105 The evaluation of technology makes the modern computer architecture consist of many processing cores. The mechanism of increasing core numbers of the computer system become the major orientation of design computer systems. As the number of processing cores are increased, the interconnection network for connecting these cores become the dominant factor of computer performance. Hence how to improve the performance of the interconnection network becomes the important goal of develop modern computer systems. The performance of interconnection network are affected by the connecting topology, routing mechanism, switch architecture, and the flow control mechanism. Accordingly, this study based on the Self Similar Cubic (SSC) multicore network, develops a new interconnection network, Alternative Self Similar Cubic (ASSC) by adding the inter-block alternative paths and the corresponding packet management mechanisms. The additional inter-block alternative paths can reduce the distance of transferring among foreign nodes. The packet management mechanisms can adjust the packet sending rates to avoid the potential packet congestion. This study firstly introduces the original SSC and the proposed ASSC interconnection networks, with the packet management mechanisms for ASSC network. Then the models of main components of ASSC interconnection network are discussed. The suitable routing mechanism and the packet management mechanisms are also implemented. These models and mechanisms are evaluated by using several kinds of packet patterns, to reveal the capabilities and performance enhancement. According to the experimental results, compared to original SSC network, the proposed ASSC network and the corresponding packet management mechanism can solve the packet congestion and improve the performance of the packet communication. Slo-Li Chu 朱守禮 2017 學位論文 ; thesis 76 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 中原大學 === 資訊工程研究所 === 105 === The evaluation of technology makes the modern computer architecture consist of many processing cores. The mechanism of increasing core numbers of the computer system become the major orientation of design computer systems. As the number of processing cores are increased, the interconnection network for connecting these cores become the dominant factor of computer performance. Hence how to improve the performance of the interconnection network becomes the important goal of develop modern computer systems. The performance of interconnection network are affected by the connecting topology, routing mechanism, switch architecture, and the flow control mechanism. Accordingly, this study based on the Self Similar Cubic (SSC) multicore network, develops a new interconnection network, Alternative Self Similar Cubic (ASSC) by adding the inter-block alternative paths and the corresponding packet management mechanisms. The additional inter-block alternative paths can reduce the distance of transferring among foreign nodes. The packet management mechanisms can adjust the packet sending rates to avoid the potential packet congestion. This study firstly introduces the original SSC and the proposed ASSC interconnection networks, with the packet management mechanisms for ASSC network. Then the models of main components of ASSC interconnection network are discussed. The suitable routing mechanism and the packet management mechanisms are also implemented. These models and mechanisms are evaluated by using several kinds of packet patterns, to reveal the capabilities and performance enhancement. According to the experimental results, compared to original SSC network, the proposed ASSC network and the corresponding packet management mechanism can solve the packet congestion and improve the performance of the packet communication.
author2 Slo-Li Chu
author_facet Slo-Li Chu
Teng-Yao Hsu
許藤耀
author Teng-Yao Hsu
許藤耀
spellingShingle Teng-Yao Hsu
許藤耀
Design Performance Enhancement Mechanisms for the On-Chip Network of the Multicore Architecture
author_sort Teng-Yao Hsu
title Design Performance Enhancement Mechanisms for the On-Chip Network of the Multicore Architecture
title_short Design Performance Enhancement Mechanisms for the On-Chip Network of the Multicore Architecture
title_full Design Performance Enhancement Mechanisms for the On-Chip Network of the Multicore Architecture
title_fullStr Design Performance Enhancement Mechanisms for the On-Chip Network of the Multicore Architecture
title_full_unstemmed Design Performance Enhancement Mechanisms for the On-Chip Network of the Multicore Architecture
title_sort design performance enhancement mechanisms for the on-chip network of the multicore architecture
publishDate 2017
url http://ndltd.ncl.edu.tw/handle/xxwjf2
work_keys_str_mv AT tengyaohsu designperformanceenhancementmechanismsfortheonchipnetworkofthemulticorearchitecture
AT xǔténgyào designperformanceenhancementmechanismsfortheonchipnetworkofthemulticorearchitecture
AT tengyaohsu shèjìshìyòngyúduōhéxīnjiàgòuzhījīngpiànhùliánwǎnglùxiàonénggǎishànjīzhì
AT xǔténgyào shèjìshìyòngyúduōhéxīnjiàgòuzhījīngpiànhùliánwǎnglùxiàonénggǎishànjīzhì
_version_ 1719150019756425216