| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 105 === This paper purpose an improvedamplifier applied to Two-Step Successive-Approximation Analog-to-Digital Converter structure technique to reduce the power of the amplifiereven the total power of the Two-Step Successive-Approximation Analog-to-Digital Converter. The use of partition circuit and then adjust the current proportion of each block and the use of Class-AB concept design output of the MOS component Q point (The dominant powerconsumption of the amplifier, also the most of power consumption of the SAR ADC), effectively improve the efficiency of the amplifierfor power supply. In addition, this paper will analyze the impact of parasitic capacitance of the circuit and summarizes an optimization design procedure of Two Step Successive-Approximation Analog-to-Digital Converters.
In this work, improve an amplifier applied to a 10-bit 20MS/s two-step successive approximation register analog to digital converter is proposed by usingthe structure of folded cascade and non-inverting amplifier. Design platform is TSMC 0.18μm 1P6M CMOS process. The gain of this work is 74.56dB, f3dB of this work is 0.36MHz, power consumption of this work is 0.9342mW at 1.8V power supply. The chip area is 84.89µm×33.83µm。
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