| Summary: | 碩士 === 華梵大學 === 電子工程學系碩士班 === 105 === Modern life can’t live without 3C electronic, application of science more widely, synonymous with lelctronic communication products are not rare luxury, in price from expensive to mean that everyone has a 3C product. In this field of electronic communications, integrated circuit has flourished, Phase-Locked Loop today has widely been used in wired and wireless communications thansmission, as the semiconductor industry, fast development the rapid maturation, The process technology also makes the more mature sophisticated integrated circuits get smaller area, now to cope with miniaturization, convenience and technology products can be added more features in the inside, consider the choice between cost and performance, In the phase-locked loop which accounted for most of the area is part of the loop filter,
the emphasis let the circuit can have a more stable and have better performance under the premise, how to reduce noise generation or circuit can be more stable the new architecture have been proposed. However, there are many ways to reduce the noise generated or accumulated, for example, using a phase-locked loop and then an additional set of voltage controlled oscillator or injection circuit, clean or injection to offset the reference phase Voltage Controlled Oscillator phase noise generated, or the injection clean reference phase to offset voltage controlled oscillatorphase noise generated.
In this thesis, Section two is produce of traditional phase-locked loop; Section three is realize the basic of phase-locked loop by TSMC 0.18μm 1P6M CMOS , Section four is design of injection-lock low noise PLL, this will reduce the voltage controlled oscillator circuit design of noise generated and faster lock; Section five is conclusion.
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