Improve Chip Side Wall Crack Issue: Using TRIZ Approach

• Main Authors: CHEN, WEN-CHUNG, 陳文中
• Other Authors: WANG, CHIA-NAN
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/59327420051140049416

碩士 === 國立高雄應用科技大學 === 工業工程與管理系碩士在職專班 === 105 === Global semiconductor output value was be more than US 330 billion dollars in 2016, and Taiwan’s assembly output value was US 12.5 billion dollars, semiconductor industry is very important in Taiwan, but we faced challenge with China recently, China has made technical support and expanded market by mergers and acquisitions. Taiwanese manufacturers need to satisfy customer’s request that improve process technical, yield rate, output. This case was wafer fab develop 28nm wafer, customer submit 28nm wafer to try run in Assembly plant. , so follow previous parameter to product for new device, QA had not find any abnormal in chip surface during operation, but last station Open/short found plenty abnormal. Cause yield rate lower than customer’s target. This case use document and archives analysis, experimental analysis, history analysis to find abnormal was side wall crack, the root cause was that laser shape was too narrow in laser grooving. This case use 39 contradiction matrix and 40 invention principles of TRIZ to solve abnormal issue, laser structure need to add wide beam mirror after discuss with vendor. Finally, to check laser shape was normal for all laser grooving machine, different wafer fab, chip side wall. Yield rate improve to 99.61%. Customer agree to keep feeding new device to product.