| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 105 === Pipeline analog-to-digital converters (ADCs) are widely applied to wireless communication, radar systems, medical imaging and data acquisition. Due to the requirement of low power consumption for portable systems and lower supply voltages with process scaling, op-amps become the bottleneck of designing pipeline ADCs. To solve this problem, previous research has proposed the use of ring amplifiers to replace conventional op-amps. The ring amplifiers are majorly constructed by inverters which have the advantage of operation under low supply voltages as well as low power consumption. With these benefits, ring amplifiers are suitable for advanced process. However, ring amplifiers usually suffer from undesirable oscillation due to their narrow stable range. In this thesis, a latch-based ring amplifier is proposed to alleviate this problem. Besides, we adopt two auto-zero schemes to relieve oscillation and common mode error accumulation. Moreover, a background calibration, which is implemented in MATLAB, is used to correct the stage-gain error of pipeline stages.
A 10-bit 70-MS/s 1.0-V non-op-amp based pipeline ADC has been carried out with TSMC standard 90-nm 1P9M CMOS process. The active area is 0.6608 mm2. Measurement results show that the power consumption is 3.65 mW when the sampling frequency is 70MS/s. The measured DNL and INL are within -0.65~0.96 LSB and -1.72~1.89 LSB at 70MS/s, respectively. The peak SNDR and SFDR are 52.06 and 63.15 dB at 0.5-MHz input
frequency, respectively. The ENOB is 8.36 bits. The FOM of this ADC at 70 MS/s is 159fJ/conversion-step.
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