Analysis and Optimization of Variable-Latency Designs in the Presence of Timing Variability
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 105 === Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations and aging effects manifest themselves...
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ndltd-TW-105NCTU53940352017-09-06T04:22:27Z http://ndltd.ncl.edu.tw/handle/09342547578752013230 Analysis and Optimization of Variable-Latency Designs in the Presence of Timing Variability 針對可變動延遲設計時序變動之分析及最佳化 Tsai, Chamg-Lin 蔡長霖 碩士 國立交通大學 資訊科學與工程研究所 105 Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations and aging effects manifest themselves as gate delay shifts, and in turn cause variability of circuit timing (timing variability). Required for dealing with the impact of timing variability better, detailed evaluation and analysis of circuit timing for VLD are actually not straightforward. In this paper, we present a systematic methodology for analyzing a VLD circuit, and identifying critical 1-cycle and 2-cycle paths/gates. Based on the criticality analysis, a gate sizing framework using particle swarm optimization (PSO) is pro-posed. Our objective is, in a less pessimistic fashion, making constructed VLD circuits better (less vulnerable to timing variability). The proposed framework is experimentally verified to be runtime-efficient and able to provide promising results. On average, an extra timing slack of 10% can be obtained without lengthening the clock period, and only 4% area overhead is introduced. Wu, Kai-Chiang 吳凱強 2016 學位論文 ; thesis 44 zh-TW |
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碩士 === 國立交通大學 === 資訊科學與工程研究所 === 105 === Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations and aging effects manifest themselves as gate delay shifts, and in turn cause variability of circuit timing (timing variability). Required for dealing with the impact of timing variability better, detailed evaluation and analysis of circuit timing for VLD are actually not straightforward. In this paper, we present a systematic methodology for analyzing a VLD circuit, and identifying critical 1-cycle and 2-cycle paths/gates. Based on the criticality analysis, a gate sizing framework using particle swarm optimization (PSO) is pro-posed. Our objective is, in a less pessimistic fashion, making constructed VLD circuits better (less vulnerable to timing variability). The proposed framework is experimentally verified to be runtime-efficient and able to provide promising results. On average, an extra timing slack of 10% can be obtained without lengthening the clock period, and only 4% area overhead is introduced.
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author2 |
Wu, Kai-Chiang |
author_facet |
Wu, Kai-Chiang Tsai, Chamg-Lin 蔡長霖 |
author |
Tsai, Chamg-Lin 蔡長霖 |
spellingShingle |
Tsai, Chamg-Lin 蔡長霖 Analysis and Optimization of Variable-Latency Designs in the Presence of Timing Variability |
author_sort |
Tsai, Chamg-Lin |
title |
Analysis and Optimization of Variable-Latency Designs in the Presence of Timing Variability |
title_short |
Analysis and Optimization of Variable-Latency Designs in the Presence of Timing Variability |
title_full |
Analysis and Optimization of Variable-Latency Designs in the Presence of Timing Variability |
title_fullStr |
Analysis and Optimization of Variable-Latency Designs in the Presence of Timing Variability |
title_full_unstemmed |
Analysis and Optimization of Variable-Latency Designs in the Presence of Timing Variability |
title_sort |
analysis and optimization of variable-latency designs in the presence of timing variability |
publishDate |
2016 |
url |
http://ndltd.ncl.edu.tw/handle/09342547578752013230 |
work_keys_str_mv |
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