A Study of Low Interfacial Traps High-k Gate Stacks and Palladium Germanide Formation for Germanium Devices

• Main Authors: Shih, An-Shih, 石安石
• Other Authors: Chien, Chao-Hsin
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/whfpu7

碩士 === 國立交通大學 === 電子研究所 === 105 === In this thesis, we found PdGe alloy junction on n-Ge had obvious electron Schottky barrier height decrement with annealing temperature raising from 300℃ to 400℃. The Schottky barrier height decrement of PdGe alloy junction on n-Ge was significant when the Pd deposition layer was thicker (Pd ≥ 50nm). The leakage current of PdGe junction on n-Ge with 400℃ PDA increased dramatically to 10^2 A/cm2. Therefore, the I-V characteristics of PdGe junction on n-Ge with 400℃ PDA showed “Ohmic-like” behavior. This behavior could be well fitted by TCAD simulation by assuming the electron Schottky barrier height was 0.57 eV along with bulk defect density was 2E19 cm-3 near mid-gap in Ge. The simulation results successfully explained the “Ohmic-like” behavior by “trap assisted tunneling” mechanism. Moreover, we further confirmed the temperature dependence of trap assisted tunneling current by low temperature measurement. The contribution of trap assisted tunneling current was strongly depended on the measurement temperature. Therefore, the I-V characteristics of PdGe junction on n-Ge at room temperature would get “Ohmic-like” behavior for 400℃ PDA. Next, we used microwave oxidation (MWO) and in-situ oxygen plasma oxidation (in-situ PO) to grow GeOx interfacial layer, and fabricated HfO2/Al2O3/GeO2/p-Ge MOSCAPs. In microwave oxidation process, the leakage current of MOSCAPs was increased significantly when the annealing temperature raised to 600℃. The XPS spectra showed that chemical oxidation state of Ge-oxide grown by oxygen plasma was closer to the ideal state (GeO2), which suggested that the ~1nm GeOx interfacial layer formed by in-situ PO had better quality than formed by MWO. Besides, we also investigated different combinations of high-k dielectric gate stacks. We found out that the trap density was reduced when HfO2 layer was deposited directly on GeOx. For the HfO2/Al2O3/HfO2/GeO2(in-situ PO)/p-Ge MOSCAPs, low Dit value of 5E11 eV-1cm-2 was obtained and could be further reduced to 3E11 eV-1cm-2 by post-metallization-annealing process. Physical characterizations such as TEM, and EDS were used to analyze the gate stack as well. During the thermal annealing process, Hf would diffuse and merge into GeOx matrix to form HfGeOx. Finally, we used the high-k gate stack mentioned above (HfO2/Al2O3/HfO2/GeO2) to fabricate MOSFETs. The S.S. of PFET was 136 mV/dec, and the Ion/Ioff ratio of drain current at VD= -1 V was around 5E4. Driving current of 11 μA/μm at VG-Vth=-0.75 V and VD=-1 V were obtained for PFET. The S.S. of NFET was 219 mV/dec, and the Ion/Ioff ratio of drain current at VD= 1 V was around 6E2. Driving current of 2.16 μA/μm at VG-Vth=0.53 V and VD=1 V were obtained for NFET. The distribution of Dit in band gap was extracted by full conductance method. The distribution trend suggested that the lowest Dit value might locate at the valence band edge. The effective hole mobility of HfO2/Al2O3/HfO2/GeO2 gate stack was higher than that of conventional HfO2/Al2O3/GeO2 gate stack.