Turbo Decoder Design using Zero Patching Scheme in Hybrid Trellis Architecture

• Main Authors: Chang, Po-Hsun, 張博珣
• Other Authors: Chang, Hsie-Chia
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/65510517411343366638

碩士 === 國立交通大學 === 電子研究所 === 105 === In recent years, the channel coding research in wireless communication targets for the high throughput transmission and low power consumption. Among the various kinds of codes, turbo codes are famous for the capacity-approaching performance. However, the traditional turbo decoder dealing with the high rate code encounters the problem of degradation of decoding speed. Since the reciprocal dual codes with code rate equaling to $1/(k+1)$ correspond to the code rate $k/(k+1)$ convolutional codes, the reciprocal dual codes can simplify the trellis while $k$ is larger than 1. On the other hand, the reciprocal dual codes are more complex when the code rate is less than $1/2$. In this thesis, the architecture of hybrid trellis controller between radix-4 conventional trellis and radix-4 reciprocal dual trellis is proposed for high speed and low complexity turbo codes. Also, to break through the limit of periodical puncture pattern in using reciprocal dual trellis, the zero patch method is proposed. In this thesis, the proposed decoder architecture is applied for LTE-A standard, which allows the 188 kinds of code length and the code rate is ranged from $1/3$ to $0.95$. Moreover, the design is fabricated in TN28HPM process, and the chip will be back in a few month. The post-layout simulations shows the proposed decoder could achieve 333Mbps at 6 iteration under 263MHz operating frequency. The core area is $1.08mm^2$, and draws 295.57mW of power with the energy efficiency of 0.148(nJ/bit/iter).