| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 105 === By exploiting the multirate re-sampling signal processing technique to design a fractional rate linear-phase FIR filter bank, the overall complexity of the sub-band DSP algorithms followed by the filter bank can be efficiently reduced. However, the applied fractional sampling rate conversions (SRCs) complicates the hardware complexity of the filter bank when implementation. In this thesis, we proposed a straightforward scheduling algorithm for fractional SRC to address the above issue. Then, a new implementation of a 10-ms, 18-band, 1/3-octave quasi-ANSI filter bank is proposed. The proposed quasi-ANSI filter bank has also been implemented in TSMC 90 nm CMOS high-VT technology. The test chip can be operated at 480 KHz to real-time process 24 KHz audio and it consumes approximately 79.9 μW (@0.9V). Comparing that with previous state-of-the-art design, the proposed quasi-ANSI filter bank not only saves approximately 15% computation complexity, in terms of multiplications per sample, and approximately 19.5% power, but also reduces approximately 13.4% of overall complexity of the sub-band DSP algorithms followed by the filter bank. Besides, we think that the fractional sampling rate conversion in the re-sampling concept may be applied on more systems in the feature. For the purpose to find the commonality of these kind structure. By our inspection, the original polyphase matrix form can be further reconstructed with an elegant and regular lattice structure. Based on lattice structure, we have proposed a programmable sampling rate convertor to realize a configurable architecture.
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