Effect of Channel Concentration and Boron Penetration on Poly-Si Junctionless Accumulation Mode FinFETs

碩士 === 國立交通大學 === 電子物理系所 === 105 === In this thesis, we used the double patterning to successfully fabricate devices, which with sub-30 nm channel dimension without the use of advanced lithography tools, implantation processes, and plasma treatments. The Pi gate (PG) poly-Si junctionless accumulatio...

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Main Authors: Chan, Yi-De, 詹宜得
Other Authors: Chao, Tien-Sheng
Format: Others
Language:en_US
Published: 2017
Online Access:http://ndltd.ncl.edu.tw/handle/u49wnr
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spelling ndltd-TW-105NCTU54290302019-05-16T00:08:09Z http://ndltd.ncl.edu.tw/handle/u49wnr Effect of Channel Concentration and Boron Penetration on Poly-Si Junctionless Accumulation Mode FinFETs 通道濃度與硼穿透對多晶矽無接面聚集型鰭式電晶體之影響 Chan, Yi-De 詹宜得 碩士 國立交通大學 電子物理系所 105 In this thesis, we used the double patterning to successfully fabricate devices, which with sub-30 nm channel dimension without the use of advanced lithography tools, implantation processes, and plasma treatments. The Pi gate (PG) poly-Si junctionless accumulation mode (JAM) FinFETs with different channel concentration (Nch) have been successfully fabricated and demonstrated. Through the material analysis, we found the devices with lower Nch have lower activation rate due to grain boundary, so the interface state easily affected the carriers and degraded the performance. As the channel dimension (Hfin × Wfin) of 35.5 nm × 26.5 nm and Nch of 5 × 1018 cm-3, the PG JAM FinFETs show the excellent electrical performance, such as steep S.S. ~ 114 mV/dec., small DIBL ~ 29 mV/V and Ion/Ioff ratio > 1×108 (VD = 1V)。 In addition to the effects of Nch, the issue of boron penetration was found on the PG JAM FinFETs by different S/D activation condition: It caused the obvious degradation and positive shift for S.S. and VTH, respectively. It can be mitigated by reducing thermal budget of the additional S/D activation. Our PG JAM FinFETs show the best S.S. ~ 92 mV/dec., DIBL ~ 20 mV/V. But this lowers the Ion due to the higher source/drain resistance. Moreover, we successfully separated and systematically quantitated these effects of charges, which resulted from boron penetration. The performance and reliability will be improved by scaling down channel dimension (sub-10 nm), rapid thermal annealing (RTA) and microwave annealing (MWA) in the future. Therefore, these devices are promising candidates for future multi-functional 3-D integrated circuit (IC) applications. Chao, Tien-Sheng 趙天生 2017 學位論文 ; thesis 53 en_US
collection NDLTD
language en_US
format Others
sources NDLTD
description 碩士 === 國立交通大學 === 電子物理系所 === 105 === In this thesis, we used the double patterning to successfully fabricate devices, which with sub-30 nm channel dimension without the use of advanced lithography tools, implantation processes, and plasma treatments. The Pi gate (PG) poly-Si junctionless accumulation mode (JAM) FinFETs with different channel concentration (Nch) have been successfully fabricated and demonstrated. Through the material analysis, we found the devices with lower Nch have lower activation rate due to grain boundary, so the interface state easily affected the carriers and degraded the performance. As the channel dimension (Hfin × Wfin) of 35.5 nm × 26.5 nm and Nch of 5 × 1018 cm-3, the PG JAM FinFETs show the excellent electrical performance, such as steep S.S. ~ 114 mV/dec., small DIBL ~ 29 mV/V and Ion/Ioff ratio > 1×108 (VD = 1V)。 In addition to the effects of Nch, the issue of boron penetration was found on the PG JAM FinFETs by different S/D activation condition: It caused the obvious degradation and positive shift for S.S. and VTH, respectively. It can be mitigated by reducing thermal budget of the additional S/D activation. Our PG JAM FinFETs show the best S.S. ~ 92 mV/dec., DIBL ~ 20 mV/V. But this lowers the Ion due to the higher source/drain resistance. Moreover, we successfully separated and systematically quantitated these effects of charges, which resulted from boron penetration. The performance and reliability will be improved by scaling down channel dimension (sub-10 nm), rapid thermal annealing (RTA) and microwave annealing (MWA) in the future. Therefore, these devices are promising candidates for future multi-functional 3-D integrated circuit (IC) applications.
author2 Chao, Tien-Sheng
author_facet Chao, Tien-Sheng
Chan, Yi-De
詹宜得
author Chan, Yi-De
詹宜得
spellingShingle Chan, Yi-De
詹宜得
Effect of Channel Concentration and Boron Penetration on Poly-Si Junctionless Accumulation Mode FinFETs
author_sort Chan, Yi-De
title Effect of Channel Concentration and Boron Penetration on Poly-Si Junctionless Accumulation Mode FinFETs
title_short Effect of Channel Concentration and Boron Penetration on Poly-Si Junctionless Accumulation Mode FinFETs
title_full Effect of Channel Concentration and Boron Penetration on Poly-Si Junctionless Accumulation Mode FinFETs
title_fullStr Effect of Channel Concentration and Boron Penetration on Poly-Si Junctionless Accumulation Mode FinFETs
title_full_unstemmed Effect of Channel Concentration and Boron Penetration on Poly-Si Junctionless Accumulation Mode FinFETs
title_sort effect of channel concentration and boron penetration on poly-si junctionless accumulation mode finfets
publishDate 2017
url http://ndltd.ncl.edu.tw/handle/u49wnr
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