| Summary: | 碩士 === 國立交通大學 === 電機工程學系 === 105 === Phase-locked loops (PLL) are widely used for many applications, such as system clock recovery and wireless- communication synthesizers. Nowadays, the strong demand of portable devices and consumer electronics make the PLL play an important role in electronic products. Moreover, converting analog circuits to digital systems has become a main development trend. Without analog passive elements, resistors and capacitances, it is much easier for designers to adapt their circuits to suit the scaling process technology. The complexity of logic circuits may cause more energy consumption and materials wasting in the manufacturing process. Therefore, power dissipation and area cost should be main concerns in digital circuit design.
In this thesis, we implement the first ADPLL by using full-custom design flow. Utilizing counters as frequency controllers and switching among different working modes can help to achieve fast locking. The design in the second chip is based on the first implementation with addition of fine phase tuning. Both DCOs with ring structures are made of digitally controlled delay elements. They can generate output clocks from 540 MHz to 1.25 GHz.
Both chips are designed to lock at 800MHz by 0.18μm CMOS process. With 1.8 V supply voltage, the power dissipation of the first ADPLL is 13.2mW with peak-to-peak jitter of 24ps and core area of 0.077 mm2. For the second chip, the peak-to-peak jitter is 21.6ps and the total power dissipation is 11.2mW in a core area of 0.081 mm2
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