All-Digital CMOS Digital-to-Time Converter with Improved Resolution

• Main Authors: LIN, YOU-TING, 林祐廷
• Other Authors: CHEN, CHUN-CHI
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/27bs52

碩士 === 國立高雄第一科技大學 === 電子工程系碩士班 === 105 === An all-digital CMOS digital-to-time converter (DTC) with improved resolution is presented in this dissertation. The circuit includes pulse generator (PG), pulse-expanding circuit (PEC) and time subtractor (TS). The main block in this architecture, PEC, is based on binary-weighted scheme which is constituted by 2-to-1 MUXs and pulse-expanding units. The improved-capacitance method is applied in this pulse-expanding unit to improve resolution and PVT variation. In addition, we improved the linearity of pulse-expanding value through symmetrical layout. The all-digital 4-bit CMOS digital-to-time converter was implemented in 0.35-µm TSMC CMOS process and occupied 0.037mm2. The resolution is simulated as 11.5ps, integral nonlinearity as 0.3LSB and the power consumption simulated at a sampling rate of 1MHz was 0.14mW.