| Summary: | 碩士 === 國立清華大學 === 電機工程學系所 === 105 === Abstract
As the communication system advances, the data of the digital transmission is growing rapidly.Therefore, the data converter plays the important role in the recent years. Also, high speed, high bandwidth and dynamic range are the future trend.
The topic of the thesis is implementing the digital to analog converter in the high speed and high bandwidth requirements. For high speed operation, the work employ the current steering data converter which the limit of the speed depends on the time constant, and is convenient in high speed application. However the mismatch between the current sources rigidly influence the static and dynamic performance for the data converter. Except for using bigger size of the device, we use the calibration for the current source instead. Before the operation for DAC, we can adjust the current for the current source one to one in the foreground calibration method which can save the area and also achieve the high accuracy.
In the implementation of the chip, my work employ the 10bit D/A converter in 65nm. The power supply is 2.5V and the differential output’s Vpp is 0.8V. The chip can split in two parts: the D/A converter, the delta sigma ADC. The D/A converter is built by the current steering DAC, and the delta sigma ADC which is used to sample the difference between current source implements in
the first order discrete time delta sigma modulator. After the calibration, SFDR can be improved from 58dB to 79dB in Fin=50M, Fs=1GS/s.
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