| Summary: | 碩士 === 國立臺灣科技大學 === 資訊工程系 === 105 === As the same binary programs can not be executed directly on processors with different ISAs (Instruction Set Architectures), binary translation is applied to translating the binary programs from one ISA to another. Nowadays indirect binary translation is the most common-used approach, which converts the source binary programs into the intermediate representation (IR) of a retargetable compiler and then uses the backend of the compiler to translate IR to the target programs.
During the process of building IR of the source programs, the registers of the source programs can be treated as normal variables and then be translated to IR. The relationship between registers still exists, this relationship affect register reallocation. If the target programs have more registers can be use, we can not examine load/store instructions to identify register spills and reduce the number of register spills
In this paper, we propose the concept of the register virtualization, the purpose of register virtualization is analyze the def-use relations of accesses of physical registers and examine load/store instructions to identify register spills, and then translate them to virtual registers. The backend of the retargetable compiler then can allocate these virtual registers onto the physical registers of the target platform. We implement register virtualization with Floating Accumulator architecture. This can facilitate the compiler utilizing the extra registers to reduce register spills.
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