A Push/Triple Push GaN Oscillator and Divide-by 2 / by 6 Injection-Locked Frequency Divider

• Main Authors: Ji-Shin Chiou, 丘濟昕
• Other Authors: Sheng-Lyang Jang
• Format: Others
• Language: en_US
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/6mbc5n

碩士 === 國立臺灣科技大學 === 電子工程系 === 105 === In the RF transceiver, Frequency synthesizer is very important, its blocks include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF),Voltage Controlled Oscillator (VCO), and Frequency Divider (FD), In order to pursue low-power, low phase noise, wide Locking range, the most important characteristics of performance are VCO and Divider,this thesis presents the design of voltage-controller oscillator (VCOs) and Injection-Locked Frequency Dividers (ILFDs). First, this thesis proposes a wide locking range ÷6 ILFD designed in the TSMC 0.18 μm BiCMOS process. The proposed current-reused ILFD is based on a low-frequency ÷2 p-core LC ILFD stacking on a high-frequency ÷3 n-core capacitive cross-coupled LC ILFD. Injection MOSFETS in ÷2 and ÷3 ILFDs are used as linear mixers. The injection signal is applied to the ÷3 ILFD first and the output is measured at ÷2 ILFD output. At power consumption Pdisp=9.396 mW, an external injected signal power of 0 dBm provides a locking range 2.04 GHz from 7.72 GHz to 9.76 GHz. The die area is 0.927 ×1.092 mm2. Secondly, we study a divide-by-2 transformer-coupled quadrature injection-locked frequency divider (QILFD) subject to injection power -21 dBm to 12 dBm. The ILFD consists of a transformer-coupled quadrature voltage controlled oscillator (QVCO) and two injection FETs, which are in parallel with the QVCO resonators for signal injection. The proposed CMOS ILFD has been implemented with the TSMC 0.18-μm CMOS technology. The QILFD has two non-overlapped locking ranges, the low-band locking range disappears at high injection power and high injection gate bias. The phase noise of the locked output spectrum is lower than that of free running QILFD in the 2 mode. Thirdly, this thesis designs a 0.25 μm GaN HEMT oscillator outputting a useful 2nd harmonic. The oscillator uses single-ended sub-oscillators configured in a balanced topology. The sub-oscillator uses transformer to provide output-to-input feedback to start the oscillation. The common nodes of the two sub-oscillators are virtual ground for the fundamental signals and provide outputs at the 2nd harmonic. The die area of the GaN HEMT oscillator is 2×1 mm2. The gate and drain biases are used to tune the oscillation frequency, they affect the low-frequency drain and gate current noises and phase noise of oscillator. The fundamental signal is at 4.3 GHz and the second harmonic signal is at 8.6 GHz. The phase noise is -119.1 dBc/Hz at the offset frequency of 1 MHz from the carrier at 8.62 GHz at the power consumption of 98 mW. Finally, we present a 0.25 μm GaN HEMT ring oscillator outputting a useful 3rd harmonic. The triple-push oscillator uses three HEMT amplifiers configured in a ring.The die area of the triple-push oscillator is 2×1 mm2. The gate and drain biases are used to tune the oscillation frequency. The third harmonic signal is at 7.6 GHz. The phase noise of -114.28 dBc/Hz at the offset frequency of 1 MHz from the carrier at 7.6 GHz at the power consumption of 386.456mW.