A Low-Power 13.5-bit Modified Sturdy MASH-21 Delta-Sigma AD Converter
碩士 === 國立臺灣科技大學 === 電機工程系 === 105 === Low-power analog-to-digital converter (ADC) plays an important role in speech and biomedical applications. It provides converted digital signal to the back-end microprocessor for further processing. There are many types of ADCs, one is the Delta-Sigma modulator...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/mp73xf |
| Summary: | 碩士 === 國立臺灣科技大學 === 電機工程系 === 105 === Low-power analog-to-digital converter (ADC) plays an important role in speech and biomedical applications. It provides converted digital signal to the back-end microprocessor for further processing.
There are many types of ADCs, one is the Delta-Sigma modulator which has a unique characteristic of shaping the quantization noise to high frequencies and conserves the desired signal in the low frequencies. The quantization noise can be removed by a low-pass filter easily. This advantage makes the Delta-Sigma modulator achieve high resolution.
This thesis presents a low-power modified sturdy-MASH-21 delta-sigma AD converter with 13.5-bit resolution. We modified the sturdy-MASH architecture by employing inverting integrators as well as the non-inverting integrator. We use inverters to replace conventional OP Amplifiers in the switch-capacitor integrator. The designed chip was fabricated in UMC 0.18um CMOS process. The chip area is 0.742mm^2. The operating voltage is set at 1 volt. The sampling frequency is set at 1.28 MHz and the system bandwidth is set to 10 kHz. Hence the over-sampling ratio is 64. The power consumption of the proposed ADC is 61uW.
Keyword: Delta-sigma Modulator, Sturdy-MASH, Switch-Capacitor Integrator, Multi-Stage noise Shaping.
|
|---|